Merge tag 'u-boot-atmel-fixes-2019.07-a' of git://git.denx.de/u-boot-atmel

[oweals/u-boot.git] / include / configs / ids8313.h

diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 61f64ebbbc07b5fd1c5e547e6e45398b5e18ec73..b1d01c58f977aa0db7c38162f1d60083f03431df 100644 (file)
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -20,23 +20,11 @@
 #define CONFIG_BOOT_RETRY_MIN          30
 #define CONFIG_RESET_TO_RETRY
 
-#define CONFIG_SYS_IMMR                0xF0000000
-
-#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT          3       /* Arbiter repeat count (0-7) */
-
 #define CONFIG_SYS_SICRH       0x00000000
 #define CONFIG_SYS_SICRL       (SICRL_LBC | SICRL_SPI_D)
 
 #define CONFIG_HWCONFIG
 
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK |\
-                                HID0_ENABLE_INSTRUCTION_CACHE |\
-                                HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2        (HID2_HBE | 0x00020000)
-
 /*
  * Definitions for initial stack pointer and data area (in DCACHE )
  */
@@ -48,26 +36,13 @@
                                         - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC           LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV         LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR            (0x00040000 |\
-                                        (0xFF << LBCR_BMT_SHIFT) |\
-                                        0xF)
-
-#define CONFIG_SYS_LBC_MRTPR           0x20000000
-
 /*
  * Internal Definitions
  */
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
 
 /*
  * Manually set up DDR parameters,
@@ -142,9 +117,6 @@
 #define CONFIG_SYS_FLASH_BASE          0xFF800000
 #define CONFIG_SYS_FLASH_SIZE          8
 
-/* FLASH */
-#define CONFIG_SYS_BR0_PRELIM          (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR0_PRELIM          (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1
 #define CONFIG_SYS_MAX_FLASH_SECT      128
@@ -163,9 +135,6 @@
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128 << 10)
 #define NAND_CACHE_PAGES               64
 
-/* NAND */
-#define CONFIG_SYS_BR1_PRELIM  (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST)
 
 /*
  * MRAM setup
@@ -175,9 +144,6 @@
 
 #define CONFIG_SYS_OR_TIMING_MRAM
 
-/* MRAM */
-#define CONFIG_SYS_BR2_PRELIM          (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET)
 
 /*
  * CPLD setup
@@ -187,9 +153,6 @@
 
 #define CONFIG_SYS_OR_TIMING_MRAM
 
-/* CPLD */
-#define CONFIG_SYS_BR3_PRELIM          (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET)
 
 /*
  * HW-Watchdog