Support for redundant environment in NAND Flash.

[oweals/u-boot.git] / include / configs / ep8260.h

diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index f14442df26097481ef37213ed883d537a1610e79..686251930918bf87afcca4ff66d5b0073a0de2cb 100644 (file)
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -26,7 +26,7 @@
 
 /*
  * board/config.h - configuration options, board specific
- * 
+ *
  * "EP8260 H, V.1.1"
  *     - 64M 60x Bus SDRAM
  *     - 32M Local Bus SDRAM
@@ -37,7 +37,7 @@
  *     - 300MHz/133MHz/66MHz
  *     - 64M 60x Bus SDRAM
  *     - 32M Local Bus SDRAM
- *     - 32M Flash 
+ *     - 32M Flash
  *     - 128k NVRAM with RTC
  */
 
@@ -48,6 +48,8 @@
 #define CFG_EP8260_H2  1
 /* #undef CFG_EP8260_H2  */
 
+#define CONFIG_CPM2            1       /* Has a CPM2 */
+
 /* What is the oscillator's (UX2) frequency in Hz? */
 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
 
@@ -104,7 +106,7 @@
 #define CFG_FLASH0_SIZE 32
 #else
 #define CFG_FLASH0_BASE 0xFF000000
-#define CFG_FLASH0_SIZE 16 
+#define CFG_FLASH0_SIZE 16
 #endif
 
 /* What should the base address of the secondary FLASH be and how big
@@ -127,7 +129,7 @@
  * local bus (8260 local bus is NOT cacheable!)
 */
 /* #define CFG_LSDRAM */
-#undef CFG_LSDRAM 
+#undef CFG_LSDRAM
 
 #ifdef CFG_LSDRAM
 /* What should be the base address of SDRAM DIMM (local bus) and how big is
@@ -260,7 +262,7 @@
 #ifdef CFG_EP8260_H2
 #define CONFIG_BAUDRATE         9600
 #else
-#define CONFIG_BAUDRATE         115200 
+#define CONFIG_BAUDRATE         115200
 #endif
 
 /* Ethernet MAC address */
@@ -297,6 +299,7 @@
                                        CFG_CMD_BSP     | \
                                        CFG_CMD_DCR     | \
                                        CFG_CMD_DHCP    | \
+                                       CFG_CMD_DISPLAY | \
                                        CFG_CMD_DOC     | \
                                        CFG_CMD_DTT     | \
                                        CFG_CMD_EEPROM  | \
@@ -463,8 +466,13 @@
 #define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 #endif
 
+#ifdef CFG_EP8260_H2
+#define CFG_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
+#define CFG_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
+#else
 #define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 #define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
+#endif
 
 #ifndef CFG_RAMBOOT
 #  define CFG_ENV_IS_IN_FLASH  1
@@ -553,9 +561,9 @@
  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  */
 #ifdef CFG_EP8260_H2
-/* TBD: Find out why setting the BMT to 0xff causes the FCC to 
- * generate TX buffer underrun errors for large packets under 
- * Linux 
+/* TBD: Find out why setting the BMT to 0xff causes the FCC to
+ * generate TX buffer underrun errors for large packets under
+ * Linux
  */
 #define CFG_SYPCR_BMT  0x00000600
 #else
@@ -604,7 +612,11 @@
  * SCCR - System Clock Control                                   9-8
  *-----------------------------------------------------------------------
  */
+#ifdef CFG_EP8260_H2
+#define CFG_SCCR        (SCCR_DFBRG00)
+#else
 #define CFG_SCCR        (SCCR_DFBRG01)
+#endif
 
 /*-----------------------------------------------------------------------
  * RCCR - RISC Controller Configuration                         13-7
@@ -742,4 +754,22 @@
 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
 
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV               "nor0"
+#define CONFIG_JFFS2_PART_SIZE         0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET       0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT         ""
+#define MTDPARTS_DEFAULT       ""
+*/
+
 #endif  /* __CONFIG_H */