#define DEBUG_PARSER
#define CONFIG_X86 1 /* Intel X86 CPU */
-#define CONFIG_SC520 1 /* AMD SC520 */
-#define CONFIG_SC520_SSI
+#define CONFIG_SYS_SC520 1 /* AMD SC520 */
+#define CONFIG_SYS_SC520_SSI
#define CONFIG_SHOW_BOOT_PROGRESS 1
#define CONFIG_LAST_STAGE_INIT 1
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_ENV /* saveenv */
+#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
-#undef CONFIG_CMD_IRQ /* IRQ Information */
+#define CONFIG_CMD_IRQ /* IRQ Information */
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
-#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */
* CPU Features
*/
#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
-#undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */
-#define CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */
-#undef CONFIG_SYS_TIMER_GENERIC /* use the i8254 PIT timers */
-#undef CONFIG_SYS_TIMER_TSC /* use the Pentium TSC timers */
+#undef CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */
+#define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */
+#undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */
+#undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */
#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
* in the SC520 on the CDP */
+#define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_NUM_IRQS 16
/*-----------------------------------------------------------------------
* Memory organization