ARM: tegra: define CONFIG_SYS_BOOTMAPSZ

[oweals/u-boot.git] / include / configs / corenet_ds.h

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 8f6f39add33bec2a993575766be007dd58d1dc42..c41b03999642e5867a979ae88e0aaff3f1ef6d62 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -31,6 +31,14 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE       CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#if defined(CONFIG_P3041DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
+#elif defined(CONFIG_P4080DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
+#elif defined(CONFIG_P5020DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#endif
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
@@ -68,10 +76,6 @@
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1                   /* SRIO port 1 */
-#define CONFIG_SRIO2                   /* SRIO port 2 */
-
 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
 
 #define CONFIG_ENV_OVERWRITE
@@ -186,11 +190,7 @@
 #define CONFIG_DDR_SPD
 #define CONFIG_FSL_DDR3
 
-#ifdef CONFIG_P3060QDS
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#else
 #define CONFIG_SYS_SPD_BUS_NUM 1
-#endif
 #define SPD_EEPROM_ADDRESS1    0x51
 #define SPD_EEPROM_ADDRESS2    0x52
 #define SPD_EEPROM_ADDRESS     SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
@@ -705,7 +705,7 @@
 
 #define CONFIG_BAUDRATE        115200
 
-#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
+#ifdef CONFIG_P4080DS
 #define __USB_PHY_TYPE ulpi
 #else
 #define __USB_PHY_TYPE utmi
@@ -714,10 +714,10 @@
 #define        CONFIG_EXTRA_ENV_SETTINGS                               \
        "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
        "bank_intlv=cs0_cs1;"                                   \
-       "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\
+       "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
        "netdev=eth0\0"                                         \
-       "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                  \
-       "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"                  \
+       "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
+       "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
        "tftpflash=tftpboot $loadaddr $uboot && "               \
        "protect off $ubootaddr +$filesize && "                 \
        "erase $ubootaddr +$filesize && "                       \