CONFIG: EXYNOS5: Enable silent console
[oweals/u-boot.git] / include / configs / coreboot.h
index a4aa8f74535e4d3f1d769e8b2c4e51759c2a840a..be04a7548a7971fa40a11fbc95ff0d6f908babf5 100644 (file)
@@ -38,9 +38,9 @@
 #define CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_LAST_STAGE_INIT
 #define CONFIG_SYS_VSNPRINTF
-#define CONFIG_INTEL_CORE_ARCH /* Sandy bridge and ivy bridge chipsets. */
 #define CONFIG_ZBOOT_32
 #define CONFIG_PHYSMEM
+#define CONFIG_SYS_EARLY_PCI_INIT
 
 #define CONFIG_LMB
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_SEPARATE
 #define CONFIG_DEFAULT_DEVICE_TREE     link
 
+#define CONFIG_BOOTSTAGE
+#define CONFIG_BOOTSTAGE_REPORT
+#define CONFIG_BOOTSTAGE_FDT
+#define CONFIG_CMD_BOOTSTAGE
+/* Place to stash bootstage data from first-stage U-Boot */
+#define CONFIG_BOOTSTAGE_STASH         0x0110f000
+#define CONFIG_BOOTSTAGE_STASH_SIZE    0x7fc
+#define CONFIG_BOOTSTAGE_USER_COUNT    60
+
+#define CONFIG_LZO
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+
 /*-----------------------------------------------------------------------
  * Watchdog Configuration
  */
 #define CONFIG_SYS_MEMTEST_END                 0x01000000
 #define CONFIG_SYS_LOAD_ADDR                   0x100000
 #define CONFIG_SYS_HZ                          1000
-#define CONFIG_SYS_X86_ISR_TIMER
 
 /*-----------------------------------------------------------------------
  * SDRAM Configuration
  * CPU Features
  */
 
-#define CONFIG_SYS_GENERIC_TIMER
+#define CONFIG_SYS_X86_TSC_TIMER
 #define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_PCAT_TIMER
 #define CONFIG_SYS_NUM_IRQS                    16
 
 /*-----------------------------------------------------------------------