Merge tag 'u-boot-atmel-fixes-2019.07-a' of git://git.denx.de/u-boot-atmel

[oweals/u-boot.git] / include / configs / cm_t35.h

diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 415924549bdb715384a16afa885f9d15f35afc66..fd693cf25141167eaa20e465bfa9288a2d075076 100644 (file)
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -30,8 +30,6 @@
 #define V_OSCK                 26000000        /* Clock output from T2 */
 #define V_SCLK                 (V_OSCK >> 1)
 
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_CMDLINE_TAG             /* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
@@ -62,7 +60,6 @@
  * select serial console configuration
  */
 #define CONFIG_SYS_NS16550_COM3                OMAP34XX_UART3
-#define CONFIG_SERIAL3                 3       /* UART3 */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -84,13 +81,10 @@
 /*
  * TWL4030
  */
-#define CONFIG_TWL4030_LED
 
 /*
  * Board NAND Info.
  */
-#define CONFIG_SYS_NAND_ADDR           NAND_BASE       /* physical address */
-                                                       /* to access nand */
 #define CONFIG_SYS_NAND_BASE           NAND_BASE       /* physical address */
                                                        /* to access nand at */
                                                        /* CS0 */
@@ -174,7 +168,6 @@
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS   1       /* CS1 is never populated */
 #define PHYS_SDRAM_1           OMAP34XX_SDRC_CS0
 
 /*-----------------------------------------------------------------------
@@ -203,7 +196,6 @@
 #define CONFIG_SPLASHIMAGE_GUARD
 
 /* Display Configuration */
-#define CONFIG_VIDEO_OMAP3
 #define LCD_BPP                LCD_COLOR16
 
 #define CONFIG_SPLASH_SCREEN
@@ -240,7 +232,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x80000
 
-#define CONFIG_SPL_TEXT_BASE           0x40200800
 #define CONFIG_SPL_MAX_SIZE            (SRAM_SCRATCH_SPACE_ADDR - \
                                         CONFIG_SPL_TEXT_BASE)