Merge branch 'master' of git://git.denx.de/u-boot-coldfire

[oweals/u-boot.git] / include / configs / canyonlands.h

diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index ec08ba7a2cb12e4250492be35cf2562f2cd342fe..d814012c415ee08e952e7397d8eff5b2f18bd902 100644 (file)
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -102,7 +102,7 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS     (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |    \
                                         (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 
-#define CONFIG_SYS_OCM_BASE            0xE3000000      /* OCM: 16k             */
+#define CONFIG_SYS_OCM_BASE            0xE3000000      /* OCM: 64k             */
 #define CONFIG_SYS_SRAM_BASE           0xE8000000      /* SRAM: 256k           */
 #define CONFIG_SYS_LOCAL_CONF_REGS     0xEF000000
 
@@ -234,7 +234,6 @@
  * NAND-FLASH related
  *----------------------------------------------------------------------*/
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define NAND_MAX_CHIPS         1
 #define CONFIG_SYS_NAND_BASE           (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 #define CONFIG_SYS_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
 
@@ -570,6 +569,16 @@
 
 #define CONFIG_SYS_EBC_CFG             0xB8400000              /*  EBC0_CFG */
 
+/*
+ * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
+ * pin multiplexing correctly
+ */
+#if defined(CONFIG_ARCHES)
+#define GPIO43_USE             GPIO_SEL        /* On Arches this pin is used as GPIO */
+#else
+#define GPIO43_USE             GPIO_ALT1       /* On Glacier this pin is used as ALT1 -> PerCS3 */
+#endif
+
 /*
  * PPC4xx GPIO Configuration
  */
@@ -698,7 +707,7 @@
 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                                */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                         */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                         */      \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)         DMAReq1         IRQ(10)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)         DMAReq1         IRQ(10)*/ \
 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)         DMAAck1         IRQ(11)*/ \
 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)         EOT/TC1         IRQ(12)*/ \
 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)    DMAReq0         IRQ(13)*/ \