ARM: socfpga: vining_fpga: Update environment

[oweals/u-boot.git] / include / configs / caddy2.h

diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index 928136f325f666002b2446a8a279691198815003..89deeac4e7dee510de795d4c68858a14ed6de761 100644 (file)
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -96,14 +96,6 @@
 #define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB */
 #define CONFIG_SYS_MALLOC_LEN          (256 * 1024)    /* Malloc size */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
 #undef CONFIG_SYS_LB_SDRAM     /* if board has SDRAM on local bus */
 
 /*
@@ -233,7 +225,6 @@
  */
 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 #define CONFIG_SYS_I2C_RTC_ADDR        0x32
-#define CONFIG_RTC_RX8025
 
 /* Pass Ethernet MAC to VxWorks */
 #define CONFIG_SYS_VXWORKS_MAC_PTR     0x000043f0