/*
* CPU configuration
*/
-#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
-
#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
#define ARC_APB_PERIPHERAL_BASE 0xF0000000
#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
/*
* Environment settings
*/
-#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE SZ_512
#define CONFIG_ENV_OFFSET 0