Enable address translation on MPC83xx

[oweals/u-boot.git] / include / configs / at91rm9200dk.h

diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index d32ec34fc2a708431864581d910d8fbc4970240b..8fad55d81cf4c36c84f7815996a2d0faeda08298 100644 (file)
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -25,12 +25,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * If we are developing, we might want to start armboot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#define CONFIG_INIT_CRITICAL
-
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK       179712000       /* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MASTER_CLOCK     59904000        /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
@@ -38,13 +32,17 @@
 
 #define AT91_SLOW_CLOCK                32768   /* slow clock */
 
-#define CONFIG_AT91RM9200DK    1       /* on an AT91RM9200DK Board      */
-#undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff */
+#define CONFIG_ARM920T         1       /* This is an ARM920T Core      */
+#define CONFIG_AT91RM9200      1       /* It's an Atmel AT91RM9200 SoC */
+#define CONFIG_AT91RM9200DK    1       /* on an AT91RM9200DK Board     */
+#undef  CONFIG_USE_IRQ                 /* we don't need IRQ/FIQ stuff  */
+#define USE_920T_MMU           1
+
 #define CONFIG_CMDLINE_TAG     1       /* enable passing of ATAGs      */
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG      1
 
-#ifdef CONFIG_INIT_CRITICAL
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define CFG_USE_MAIN_OSCILLATOR                1
 /* flash */
 #define MC_PUIA_VAL    0x00000000
@@ -74,7 +72,7 @@
 #define SDRC_MR_VAL2   0x00000003 /* Load Mode Register */
 #define SDRC_MR_VAL3   0x00000000 /* Normal Mode */
 #define SDRC_TR_VAL    0x000002E0 /* Write refresh rate */
-#endif /* CONFIG_INIT_CRITICAL */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 /*
  * Size of malloc() pool
  */
@@ -83,8 +81,6 @@
 
 #define CONFIG_BAUDRATE 115200
 
-#define CFG_AT91C_BRGR_DIVISOR 33      /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
-
 /*
  * Hardware drivers
  */
@@ -102,7 +98,7 @@
 /* #define CONFIG_ENV_OVERWRITE        1 */
 
 #define CONFIG_COMMANDS                \
-                      ((CONFIG_CMD_DFL | \
+                      ((CONFIG_CMD_DFL | CFG_CMD_MII |\
                        CFG_CMD_DHCP ) & \
                      ~(CFG_CMD_BDI | \
                        CFG_CMD_IMI | \
@@ -177,19 +173,19 @@
 #define CFG_ENV_SIZE                   0x2000  /* 0x8000 */
 #else
 #define CFG_ENV_IS_IN_FLASH            1
-#ifdef CONFIG_INIT_CRITICAL
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
 #define CFG_ENV_ADDR                   (PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
 #define CFG_ENV_SIZE                   0x10000 /* sectors are 64K here */
 #else
 #define CFG_ENV_ADDR                   (PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
 #define CFG_ENV_SIZE                   0x2000  /* 0x8000 */
-#endif /* CONFIG_INIT_CRITICAL */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 #endif /* CFG_ENV_IS_IN_DATAFLASH */
 
 
 #define CFG_LOAD_ADDR          0x21000000  /* default load address */
 
-#ifdef CONFIG_INIT_CRITICAL
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
 #define CFG_BOOT_SIZE          0x00 /* 0 KBytes */
 #define CFG_U_BOOT_BASE                PHYS_FLASH_1
 #define CFG_U_BOOT_SIZE                0x60000 /* 384 KBytes */
@@ -197,7 +193,7 @@
 #define CFG_BOOT_SIZE          0x6000 /* 24 KBytes */
 #define CFG_U_BOOT_BASE                (PHYS_FLASH_1 + 0x10000)
 #define CFG_U_BOOT_SIZE                0x10000 /* 64 KBytes */
-#endif /* CONFIG_INIT_CRITICAL */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 #define CFG_BAUDRATE_TABLE     {115200 , 19200, 38400, 57600, 9600 }