Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

[oweals/u-boot.git] / include / configs / XPEDITE5370.h

diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index acb62ad1dd4dc0750e2c16c89a646d4c167d6e8e..fc4a986039a59242fd277dd52739839de3464fc4 100644 (file)
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -36,9 +36,7 @@
 #define CONFIG_MPC8572         1
 #define CONFIG_XPEDITE5370     1
 #define CONFIG_SYS_BOARD_NAME  "XPedite5370"
-#define CONFIG_NUM_CPUS                2       /* 2 Cores */
 #define CONFIG_BOARD_EARLY_INIT_R      /* Call board_pre_init */
-#define CONFIG_RELOC_FIXUP_WORKS       /* Fully relocate to SDRAM */
 
 #define CONFIG_PCI             1       /* Enable PCI/PCIE */
 #define CONFIG_PCI_PNP         1       /* do pci plug-and-play */
@@ -49,6 +47,14 @@
 #define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCIE_RESET  1       /* need PCIe reset errata */
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
+#define CONFIG_FSL_ELBC                1
+
+/*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR  0xee000000      /* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR            /* Don't leave BPTR enabled */
 
 /*
  * DDR config
@@ -93,8 +99,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR             0xef000000      /* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS        CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR + 0xa000)
-#define CONFIG_SYS_PCIE2_ADDR          (CONFIG_SYS_CCSRBAR + 0x9000)
 
 /*
  * Diagnostics
@@ -111,13 +115,14 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xe000_0000 0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
  * 0xe800_0000 0xe87f_ffff     PCIe1 IO                8M non-cacheable
  * 0xe880_0000 0xe8ff_ffff     PCIe2 IO                8M non-cacheable
+ * 0xee00_0000 0xee00_ffff     Boot page translation   4K non-cacheable
  * 0xef00_0000 0xef0f_ffff     CCSR/IMMR               1M non-cacheable
  * 0xef80_0000 0xef8f_ffff     NAND Flash              1M non-cacheable
  * 0xf000_0000 0xf7ff_ffff     NOR Flash 2             128M non-cacheable
  * 0xf800_0000 0xffff_ffff     NOR Flash 1             128M non-cacheable
  */
 
-#define CONFIG_SYS_LBC_LCRR    (LCRR_CLKDIV_4 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR    (LCRR_CLKDIV_8 | LCRR_EADC_3)
 
 /*
  * NAND flash configuration
@@ -238,9 +243,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_OF_BOARD_SETUP          1
 #define CONFIG_OF_STDOUT_VIA_ALIAS     1
 
-#define CONFIG_SYS_64BIT_VSPRINTF      1
-#define CONFIG_SYS_64BIT_STRTOUL       1
-
 /*
  * I2C
  */
@@ -393,6 +395,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
 
 /*
  * Miscellaneous configurable options