Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[oweals/u-boot.git] / include / configs / TQM85xx.h

diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 2d4048a92835fc1cec8f095cac68a2982adcde80..2ef24cd7e506603e5b0fd825c1d5fe5d135c0ee6 100644 (file)
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -41,14 +41,21 @@
 #define CONFIG_E500            1       /* BOOKE e500 family            */
 #define CONFIG_MPC85xx         1       /* MPC8540/60/55/41             */
 
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+#define CONFIG_TQM8548
+#endif
+
 #define CONFIG_PCI
+#ifndef CONFIG_TQM8548_AG
+#define CONFIG_PCI1                    /* PCI/PCI-X controller         */
+#endif
+#ifdef CONFIG_TQM8548
+#define CONFIG_PCIE1                   /* PCI Express interface        */
+#endif
+
 #define CONFIG_FSL_PCI_INIT    1       /* Use common FSL init code     */
 #define CONFIG_PCIX_CHECK              /* PCIX olny works at 66 MHz    */
-#ifdef CONFIG_TQM8548
-#define CONFIG_PCI1
-#define CONFIG_PCIE1
 #define CONFIG_FSL_PCIE_RESET  1       /* need PCIe reset errata       */
-#endif
 
 #define CONFIG_TSEC_ENET               /* tsec ethernet support        */
 
@@ -70,7 +77,9 @@
  * Warning: NAND support will likely increase the U-Boot image size
  * to more than 256 KB. Please adjust TEXT_BASE if necessary.
  */
-#undef CONFIG_NAND
+#ifdef CONFIG_TQM8548_BE
+#define CONFIG_NAND
+#endif
 
 /*
  * MPC8540 and MPC8548 don't have CPM module
@@ -81,7 +90,9 @@
 
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code     */
 
-#undef CONFIG_CAN_DRIVER               /* CAN Driver support           */
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+#define        CONFIG_CAN_DRIVER               /* CAN Driver support           */
+#endif
 
 /*
  * sysclk for MPC85xx
@@ -106,7 +117,6 @@
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache              */
 #define CONFIG_BTB                     /* toggle branch predition      */
-#define CONFIG_ADDR_STREAMING          /* toggle addr streaming        */
 
 #define CONFIG_SYS_INIT_DBCR DBCR_IDM          /* Enable Debug Exceptions      */
 
@@ -136,6 +146,9 @@
  */
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#ifdef CONFIG_TQM8548_AG
+#define CONFIG_VERY_BIG_RAM
+#endif
 
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
@@ -234,7 +247,6 @@
 #define CONFIG_SYS_LBC_LSRT            0x20000000      /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR           0x20000000      /* LB refresh timer presc.*/
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       (CONFIG_SYS_CCSRBAR \
                                 + 0x04010000)  /* Initial RAM address  */
@@ -359,36 +371,17 @@
 #define        CONFIG_SYS_NAND_CS_DIST 0x200
 
 #define CONFIG_SYS_NAND_SIZE           0x8000
-#define CONFIG_SYS_NAND0_BASE          (CONFIG_SYS_CCSRBAR + 0x03010000)
-#define CONFIG_SYS_NAND1_BASE          (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND2_BASE          (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND3_BASE          (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE     2       /* Max number of NAND devices   */
-#define NAND_MAX_CHIPS         1
-
-#if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
-#elif (CONFIG_SYS_MAX_NAND_DEVICE == 2)
-#define        CONFIG_SYS_NAND_QUIET_TEST      1
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
-                            CONFIG_SYS_NAND1_BASE, \
-}
-#elif (CONFIG_SYS_MAX_NAND_DEVICE == 4)
-#define        CONFIG_SYS_NAND_QUIET_TEST      1
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
-                            CONFIG_SYS_NAND1_BASE, \
-                            CONFIG_SYS_NAND2_BASE, \
-                            CONFIG_SYS_NAND3_BASE, \
-}
-#endif
+#define CONFIG_SYS_NAND_BASE           (CONFIG_SYS_CCSRBAR + 0x03010000)
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices   */
+#define CONFIG_SYS_NAND_MAX_CHIPS      2       /* Number of chips per device   */
 
 /* CS3 for NAND Flash */
-#define CONFIG_SYS_BR3_PRELIM          ((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \
-                                BR_MS_UPMB | BR_V)
+#define CONFIG_SYS_BR3_PRELIM          ((CONFIG_SYS_NAND_BASE & BR_BA) | \
+                                        BR_PS_8 | BR_MS_UPMB | BR_V)
 #define CONFIG_SYS_OR3_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
 
-#define NAND_BIG_DELAY_US       25     /* max tR for Samsung devices   */
+#define NAND_BIG_DELAY_US              25      /* max tR for Samsung devices   */
 
 #endif /* CONFIG_NAND */
 
@@ -586,14 +579,14 @@
 
 #define        CONFIG_JFFS2_NAND       1
 
-#ifdef CONFIG_JFFS2_CMDLINE
+#ifdef CONFIG_CMD_MTDPARTS
 #define MTDIDS_DEFAULT         "nand0=TQM85xx-nand"
 #define MTDPARTS_DEFAULT       "mtdparts=TQM85xx-nand:-"
 #else
 #define CONFIG_JFFS2_DEV       "nand0" /* NAND device jffs2 lives on   */
 #define CONFIG_JFFS2_PART_OFFSET 0     /* start of jffs2 partition     */
 #define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition     */
-#endif /* CONFIG_JFFS2_CMDLINE */
+#endif /* CONFIG_CMD_MTDPARTS */
 
 #endif /* CONFIG_NAND */
 
@@ -607,7 +600,9 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_SNTP
+#ifndef CONFIG_TQM8548_AG
 #define CONFIG_CMD_DATE
+#endif
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_MII