ppc4xx: Add CONFIG_PCI_4xx_PTM_OVERWRITE to some esd 4xx boards

[oweals/u-boot.git] / include / configs / TQM834x.h

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index d4b0f9c9300931ad27f3818f2a19e8e7f8eb512f..da08b7c21344b122da330540efd8bfe34501a7e8 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -32,8 +32,8 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300            1       /* E300 Family */
-#define CONFIG_MPC83XX         1       /* MPC83XX family */
-#define CONFIG_MPC834X         1       /* MPC834X specific */
+#define CONFIG_MPC83xx         1       /* MPC83xx family */
+#define CONFIG_MPC834x         1       /* MPC834x specific */
 #define CONFIG_MPC8349         1       /* MPC8349 specific */
 #define CONFIG_TQM834X         1       /* TQM834X board specific */
 
@@ -78,13 +78,12 @@
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI                           /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER                        /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER                                /* use the CFI driver */
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_BASE          0x80000000      /* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE          8               /* FLASH size in MB */
-
-/* buffered writes in the AMD chip set is not supported yet */
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_EMPTY_INFO                    /* print 'E' for empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /*
  * FLASH bank number detection
@@ -251,9 +250,12 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
 /* PCI1 host bridge */
-#define CONFIG_SYS_PCI1_MEM_BASE       0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BASE       0x90000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE      (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS      CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE      0x10000000     /* 256M */
 #define CONFIG_SYS_PCI1_IO_BASE        0xe2000000
 #define CONFIG_SYS_PCI1_IO_PHYS        CONFIG_SYS_PCI1_IO_BASE
 #define CONFIG_SYS_PCI1_IO_SIZE        0x1000000       /* 16M */
@@ -419,10 +421,10 @@ extern int tqm834x_num_flash_banks;
 #ifdef CONFIG_PCI
 #define CONFIG_SYS_IBAT3L      (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT3U      (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U      (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U      (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT5L      (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT3L      (0)
 #define CONFIG_SYS_IBAT3U      (0)
@@ -535,6 +537,8 @@ extern int tqm834x_num_flash_banks;
  */
 /* mtdparts command line support */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE              /* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT         "nor0=TQM834x-0"
 
 /* default mtd partition table */