Enable address translation on MPC83xx

[oweals/u-boot.git] / include / configs / TQM834x.h

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index d434eb75999a8bbf2961281b1f478888e9de2a8f..cec7e3ece445d26ee6e7510958411c325705dab4 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -95,14 +95,14 @@
  * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
  * banks has to be determined at runtime and stored in a gloabl variable
  * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
- * used insted of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
+ * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
  * should be made sufficiently large to accomodate the number of banks that
- * might acutally be detected.  Since most (all?) Flash related functions use
+ * might actually be detected.  Since most (all?) Flash related functions use
  * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
  * defined as tqm834x_num_flash_banks.
  */
 #define CFG_MAX_FLASH_BANKS_DETECT     2
-#ifndef __ASSEMBLY__ 
+#ifndef __ASSEMBLY__
 extern int tqm834x_num_flash_banks;
 #endif
 #define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
@@ -249,7 +249,7 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_MPC83XX_TSEC1_NAME      "TSEC0"
 #define CONFIG_MPC83XX_TSEC2           1
 #define CONFIG_MPC83XX_TSEC2_NAME      "TSEC1"
-#define TSEC1_PHY_ADDR                 0
+#define TSEC1_PHY_ADDR                 2
 #define TSEC2_PHY_ADDR                 1
 #define TSEC1_PHYIDX                   0
 #define TSEC2_PHYIDX                   0
@@ -417,11 +417,58 @@ extern int tqm834x_num_flash_banks;
        HRCWH_TSEC2M_IN_GMII )
 #endif
 
+/* System IO Config */
+#define CFG_SICRH      SICRH_TSOBI1
+#define CFG_SICRL      SICRL_LDP_A
+
 /* i-cache and d-cache disabled */
 #define CFG_HID0_INIT          0x000000000
 #define CFG_HID0_FINAL         CFG_HID0_INIT
 #define CFG_HID2               0x000000000
 
+/* DDR 0 - 512M */
+#define CFG_IBAT0L     (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U     (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L     (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U     (CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 512M (no backing mem) */
+#define CFG_IBAT2L     (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U     (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI */
+#define CFG_IBAT3L     (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U     (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L     (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4U     (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L     (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U     (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+
+/* IMMRBAR */
+#define CFG_IBAT6L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U     (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+
+/* FLASH */
+#define CFG_IBAT7L     (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U     (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L     CFG_IBAT0L
+#define CFG_DBAT0U     CFG_IBAT0U
+#define CFG_DBAT1L     CFG_IBAT1L
+#define CFG_DBAT1U     CFG_IBAT1U
+#define CFG_DBAT2L     CFG_IBAT2L
+#define CFG_DBAT2U     CFG_IBAT2U
+#define CFG_DBAT3L     CFG_IBAT3L
+#define CFG_DBAT3U     CFG_IBAT3U
+#define CFG_DBAT4L     CFG_IBAT4L
+#define CFG_DBAT4U     CFG_IBAT4U
+#define CFG_DBAT5L     CFG_IBAT5L
+#define CFG_DBAT5U     CFG_IBAT5U
+#define CFG_DBAT6L     CFG_IBAT6L
+#define CFG_DBAT6U     CFG_IBAT6U
+#define CFG_DBAT7L     CFG_IBAT7L
+#define CFG_DBAT7U     CFG_IBAT7U
+
 /*
  * Internal Definitions
  *
@@ -472,17 +519,17 @@ extern int tqm834x_num_flash_banks;
        "netdev=eth0\0"                                                 \
        "hostname=tqm83xx\0"                                            \
        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
-               "nfsroot=$(serverip):$(rootpath)\0"                     \
+               "nfsroot=${serverip}:${rootpath}\0"                     \
        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
-       "addip=setenv bootargs $(bootargs) "                            \
-               "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
-               ":$(hostname):$(netdev):off panic=1\0"                  \
-       "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+       "addip=setenv bootargs ${bootargs} "                            \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+               ":${hostname}:${netdev}:off panic=1\0"                  \
+       "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
        "flash_nfs=run nfsargs addip addtty;"                           \
-               "bootm $(kernel_addr)\0"                                \
+               "bootm ${kernel_addr}\0"                                \
        "flash_self=run ramargs addip addtty;"                          \
-               "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
-       "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"     \
+               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+       "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
                "bootm\0"                                               \
        "rootpath=/opt/eldk/ppc_6xx\0"                                  \
        "bootfile=/tftpboot/tqm83xx/uImage\0"                           \