Merge branch 'master' of git://git.denx.de/u-boot-nios

[oweals/u-boot.git] / include / configs / TQM834x.h

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index efade69ca215da0b73bf1976c0e03b14401f8223..4c909e61ad0cb1010c6fef9c7cdfce3f179d17d2 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -52,7 +52,8 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR                (LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
 
 /* board pre init: do not call, nothing to do */
 #undef CONFIG_BOARD_EARLY_INIT_F
@@ -250,9 +251,12 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
 /* PCI1 host bridge */
-#define CONFIG_SYS_PCI1_MEM_BASE       0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BASE       0x90000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE      (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS      CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE      0x10000000     /* 256M */
 #define CONFIG_SYS_PCI1_IO_BASE        0xe2000000
 #define CONFIG_SYS_PCI1_IO_PHYS        CONFIG_SYS_PCI1_IO_BASE
 #define CONFIG_SYS_PCI1_IO_SIZE        0x1000000       /* 16M */
@@ -418,10 +422,10 @@ extern int tqm834x_num_flash_banks;
 #ifdef CONFIG_PCI
 #define CONFIG_SYS_IBAT3L      (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT3U      (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U      (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U      (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT5L      (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT3L      (0)
 #define CONFIG_SYS_IBAT3U      (0)