ppc4xx: Big header cleanup, mostly PPC440 related

[oweals/u-boot.git] / include / configs / PPChameleonEVB.h

diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 44f03dc3906eae9a1ad499df70bd488188d0d76b..09f3544ae0711c670803245ef5584c4dc7e0b36d 100644 (file)
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -577,17 +577,6 @@
 #define                DIMM_READ_ADDR 0xAB
 #define                DIMM_WRITE_ADDR 0xAA
 
-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register              */
-#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register       */
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register          */
-#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register    */
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register              */
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register            */
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register              */
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register                 */
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                                */
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register             */
-
 /* Defines for CPC0_PLLMR1 Register fields */
 #define PLL_ACTIVE             0x80000000
 #define CPC0_PLLMR1_SSCS       0x80000000