/*
* FPGA stuff
*/
-#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
-#define CONFIG_SYS_FPGA_MAX_SIZE (32 * 1024) /* 32kByte for CPLD */
-
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */