Support for redundant environment in NAND Flash.

[oweals/u-boot.git] / include / configs / PLU405.h

diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 73a788543541d362e1d4e48227eb2a2cca0f2c21..dd5d83168042f121c85a6c7938e2234bfabcb2d9 100644 (file)
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -160,6 +160,8 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
 #define SECTORSIZE 512
 
@@ -212,7 +214,7 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
@@ -330,7 +332,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                16384   /* For IBM 405 CPUs, older 405 ppc's    */
+#define CFG_DCACHE_SIZE                16384   /* For AMCC 405 CPUs, older 405 ppc's   */
                                        /* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)