Support for redundant environment in NAND Flash.

[oweals/u-boot.git] / include / configs / PCI405.h

diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 49fdfdddae90e83033244110256027e55806f1bf..9d5c4f4d04e7eac95f133d0ed41760cd77ece19a 100644 (file)
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2004
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -32,6 +32,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
+#define CONFIG_IDENT_STRING     " $Name: esd_PCI405_05_07_28 $"
 
 #define CONFIG_405GP           1       /* This is a PPC405 CPU         */
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
@@ -42,27 +43,21 @@
 
 #define CONFIG_SYS_CLK_FREQ    25000000 /* external frequency to pll   */
 
+#define CONFIG_BOARD_TYPES     1       /* support board types          */
+
 #define CONFIG_BAUDRATE                115200
-#define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
-
-#if 0
-#define CONFIG_PREBOOT                                                         \
-       "crc32 f0207004 ffc 0;"                                                 \
-       "if cmp 0 f0207000 1;"                                                  \
-       "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
-       "else;echo Old CRC is bad;fi"
-#endif
+#define CONFIG_BOOTDELAY       0       /* autoboot after 0 seconds     */
 
 #undef CONFIG_BOOTARGS
-#if 1
-#define CONFIG_BOOTCOMMAND                                                     \
-       "bootm fffc0000"
-#else
-#define CONFIG_BOOTCOMMAND                                                     \
-       "mw.l 0 ffffffff; mw.l 4 ffffffff;"                                     \
-       "while cmp 0 4 1; do echo Waiting for Host...;done;"                    \
-       "bootm 400000"
-#endif
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "mem_linux=14336k\0"                                            \
+       "optargs=panic=0\0"                                             \
+       "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"     \
+       "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
+       ""
+#define        CONFIG_BOOTCOMMAND      "run ramargs;run addcon;loadpci"
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
@@ -246,7 +241,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                8192    /* For IBM 405 CPUs                     */
+#define CFG_DCACHE_SIZE                8192    /* For AMCC 405 CPUs                    */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
@@ -321,16 +316,33 @@
 #define CFG_FPGA_DATA          0x01000000  /* FPGA data pin (ppc output)    */
 #define CFG_FPGA_INIT          0x00400000  /* FPGA init pin (ppc input)     */
 #define CFG_FPGA_DONE          0x00800000  /* FPGA done pin (ppc input)     */
+/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
+#define CFG_FPGA_INIT_V12      0x00008000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE_V12      0x00010000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
+#if 0 /* test-only */
 #define CFG_INIT_DCACHE_CS     7       /* use cs # 7 for data cache memory    */
 #define CFG_INIT_RAM_ADDR      0x40000000  /* use data cache                  */
 #define CFG_INIT_RAM_END       0x2000  /* End of used area in RAM             */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+#else
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM       1
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR      0xF8000000
+#define CFG_OCM_DATA_SIZE      0x1000
+#define CFG_INIT_RAM_ADDR      CFG_OCM_DATA_ADDR /* inside of SDRAM            */
+#define CFG_INIT_RAM_END       CFG_OCM_DATA_SIZE /* End of used area in RAM    */
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+#endif
 
 /*
  * Internal Definitions