Merge tag 'efi-2020-07-rc2-4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

[oweals/u-boot.git] / include / configs / P1023RDB.h

diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 1863bec33c763e762d753515df2efb3c051f9592..2f3831e2599281a7bbe0d20dd618fce2bdfe6c00 100644 (file)
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -1,19 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
  *          Chunhe Lan <Chunhe.Lan@freescale.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE   0xeff40000
-#endif
-
 #ifndef CONFIG_SYS_MONITOR_BASE
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
 #endif
@@ -23,14 +18,12 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_MP              /* support multiple processors */
 
 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
 #define CONFIG_PCIE1           /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2           /* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3           /* PCIE controller 3 (slot 3) */
 #define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET  /* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 
 #ifndef __ASSEMBLY__
@@ -49,9 +42,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_ENABLE_36BIT_PHYS
 
-#define CONFIG_SYS_MEMTEST_START       0x01000000      /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END         0x02000000
-
 /* Implement conversion of addresses in the LBC */
 #define CONFIG_SYS_LBC_LBCR            0x00000000
 #define CONFIG_SYS_LBC_LCRR            LCRR_CLKDIV_8
@@ -65,7 +55,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CHIP_SELECTS_PER_CTRL   1
 
 #define CONFIG_DDR_SPD
-#define CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SYS_SDRAM_SIZE          512u    /* DDR is 512M */
 #define CONFIG_SYS_SPD_BUS_NUM          0
 #define SPD_EEPROM_ADDRESS              0x50
@@ -98,16 +87,12 @@ extern unsigned long get_clock_freq(void);
                                | BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
 
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      512     /* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 
-#define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
-
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR       0xffd00000      /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_SIZE       0x00004000/* Size of used area in RAM */
@@ -147,7 +132,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 
 /* Serial Port */
-#define CONFIG_CONS_INDEX              1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
@@ -227,10 +211,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
-
 #define CONFIG_LOADS_ECHO              /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   /* allow baudrate change */
 
@@ -248,8 +228,6 @@ extern unsigned long get_clock_freq(void);
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING         /* Command-line editing */
 #define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
 
 /*
@@ -296,14 +274,8 @@ extern unsigned long get_clock_freq(void);
 /* For FM */
 #define CONFIG_SYS_DPAA_FMAN
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHY_ATHEROS
-#endif
-
 /* Default address of microcode for the Linux Fman driver */
 /* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR        0xEFF00000
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000
 #define CONFIG_SYS_FDT_PAD             (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
@@ -313,7 +285,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
 
 #define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC1"
 #endif