#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_NETVIA 1 /* ...on a NetVia board */
-#undef CONFIG_NETVIA_PLL_CLOCK /* PLL or fixed crystal clock */
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-#ifdef CONFIG_NETVIA_PLL_CLOCK
-/* XXX make sure that you calculate these two correctly */
-#define CFG_GCLK_MF 1350
-#define CONFIG_8xx_GCLK_FREQ 44236800
-#else
-#define CFG_GCLK_MF 1
-#define CONFIG_8xx_GCLK_FREQ 50000000
-#endif
+#define CONFIG_XIN 10000000
+#define CONFIG_8xx_GCLK_FREQ 80000000
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
-#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND)
-#else
-#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE
+#define CONFIG_CMD_NAND
#endif
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*
- */
-
-#define CFG_PLPRCR ( ((CFG_GCLK_MF-1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
+
#define SCCR_MASK SCCR_EBDF11
+
+#if CONFIG_8xx_GCLK_FREQ == 50000000
+
+#define CFG_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#define CFG_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
+#elif CONFIG_8xx_GCLK_FREQ == 80000000
+
+#define CFG_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CFG_SCCR (SCCR_TBS | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00 | SCCR_EBDF01)
+
+#endif
+
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
/*****************************************************************************/
+#define CONFIG_NAND_LEGACY
+
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* NAND */
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#endif
-/****************************************************************/
+/*************************************************************************************************/
#endif /* __CONFIG_H */