#ifndef __CONFIG_H
#define __CONFIG_H
+#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
+#error Unsupported CONFIG_NETPHONE version
+#endif
+
/*
* High Level Configuration Options
* (easy to change)
/* #define CONFIG_XIN 10000000 */
#define CONFIG_XIN 50000000
-#define MPC8XX_HZ 120000000
+/* #define MPC8XX_HZ 120000000 */
+#define MPC8XX_HZ 66666666
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "tftpboot; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#define CONFIG_AUTOSCRIPT
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
+#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
#define FEC_ENET 1 /* eth.c needs it that way... */
#undef CFG_DISCOVER_PHY
#define CONFIG_MII 1
+#define CONFIG_MII_INIT 1
#define CONFIG_RMII 1 /* use RMII interface */
#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
+#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
#define CONFIG_FEC1_PHY_NORXERR 1
#define CONFIG_ETHER_ON_FEC2 1
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
- CFG_CMD_CDP \
- )
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CDP
+
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
/*
* Miscellaneous configurable options
*/
#define CFG_HUSH_PARSER 1
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#if CONFIG_NETPHONE_VERSION == 2
+#define CFG_FLASH_BASE4 0x40080000
+#endif
+
+#define CFG_RESET_ADDRESS 0x80000000
/*
* For booting Linux, the board info and command line data
/*-----------------------------------------------------------------------
* FLASH organization
*/
+#if CONFIG_NETPHONE_VERSION == 1
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#elif CONFIG_NETPHONE_VERSION == 2
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#endif
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 50000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 25000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 40000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 75000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 10MHz
#endif
#if MPC8XX_HZ == 120000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
#elif MPC8XX_HZ == 100000000
#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
(0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
+ PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 66666666
+#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+ PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 50MHz
#endif
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
*/
#define SCCR_MASK SCCR_EBDF11
#if MPC8XX_HZ > 66666666
-#define CFG_SCCR (SCCR_TBS | \
+#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00 | SCCR_EBDF01)
#else
-#define CFG_SCCR (SCCR_TBS | \
+#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+#if CONFIG_NETPHONE_VERSION == 2
+
+#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
+
+#define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#endif
+
/*
* BR3 and OR3 (SDRAM)
*
#define DSP_SIZE 0x00010000 /* 64K */
#define NAND_SIZE 0x00010000 /* 64K */
-#define ER_SIZE 0x00010000 /* 64K */
#define DSP_BASE 0xF1000000
#define NAND_BASE 0xF1010000
-#define ER_BASE 0xF1020000
/****************************************************************/
/* NAND */
+#define CFG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
#define CFG_MAX_NAND_DEVICE 1
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
} while(0)
+#if CONFIG_NETPHONE_VERSION == 1
#define NAND_WAIT_READY(nand) \
do { \
+ int _tries = 0; \
while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
- ; \
+ if (++_tries > 100000) \
+ break; \
} while (0)
+#elif CONFIG_NETPHONE_VERSION == 2
+#define NAND_WAIT_READY(nand) \
+ do { \
+ int _tries = 0; \
+ while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
+ if (++_tries > 100000) \
+ break; \
+ } while (0)
+#endif
#define WRITE_NAND_COMMAND(d, adr) \
do { \
/*****************************************************************************/
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
+/*****************************************************************************/
+
+#if CONFIG_NETPHONE_VERSION == 1
#define STATUS_LED_BIT 0x00000008 /* bit 28 */
+#elif CONFIG_NETPHONE_VERSION == 2
+#define STATUS_LED_BIT 0x00000080 /* bit 24 */
+#endif
+
#define STATUS_LED_PERIOD (CFG_HZ / 2)
#define STATUS_LED_STATE STATUS_LED_BLINKING
/***********************************************************************************************************
+ ----------------------------------------------------------------------------------------------
+
+ (V1) version 1 of the board
+ (V2) version 2 of the board
+
+ ----------------------------------------------------------------------------------------------
+
Pin definitions:
+------+----------------+--------+------------------------------------------------------------
| PB30 | SPI_CLK | Output | SPI Clock
| PC10 | DISPA0 | Output | Display A0
| PC11 | BACKLIGHT | Output | Display backlit
- | PC12 | SPI2RXD | Input | 2nd SPI RXD
- | PC13 | SPI2TXD | Output | 2nd SPI TXD
- | PC15 | SPI2CLK | Output | 2nd SPI CLK
+ | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
+ | | IO_RESET | Output | (V2) General I/O reset
+ | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
+ | | HOOK | Input | (V2) Hook input interrupt
+ | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
+ | | F_RY_BY | Input | (V2) NAND F_RY_BY
| PE17 | F_ALE | Output | NAND F_ALE
| PE18 | F_CLE | Output | NAND F_CLE
| PE20 | F_CE | Output | NAND F_CE
- | PE24 | SPICS_SCOUT | Output | Codec chip select
+ | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
+ | | LED | Output | (V2) LED
| PE27 | SPICS_ER | Output | External serial register CS
- | PE28 | LEDIO1 | Output | LED
- | PE29 | LEDIO2 | Output | LED hook for A (TA2)
- | PE30 | LEDIO3 | Output | LED hook for A (TA2)
- | PE31 | F_RY_BY | Input | NAND F_RY_BY
+ | PE28 | LEDIO1 | Output | (V1) LED
+ | | BKBR1 | Input | (V2) Keyboard input scan
+ | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
+ | | BKBR2 | Input | (V2) Keyboard input scan
+ | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
+ | | BKBR3 | Input | (V2) Keyboard input scan
+ | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
+ | | BKBR4 | Input | (V2) Keyboard input scan
+------+----------------+--------+---------------------------------------------------
+ ----------------------------------------------------------------------------------------------
+
+ Serial register input:
+
+ +------+----------------+------------------------------------------------------------
+ | # | Name | Comment
+ +------+----------------+------------------------------------------------------------
+ | 0 | BKBR1 | (V1) Keyboard input scan
+ | 1 | BKBR3 | (V1) Keyboard input scan
+ | 2 | BKBR4 | (V1) Keyboard input scan
+ | 3 | BKBR2 | (V1) Keyboard input scan
+ | 4 | HOOK | (V1) Hook switch
+ | 5 | BT_LINK | (V1) Bluetooth link status
+ | 6 | HOST_WAKE | (V1) Bluetooth host wake up
+ | 7 | OK_ETH | (V1) Cisco inline power OK status
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Serial register output:
+
+ +------+----------------+------------------------------------------------------------
+ | # | Name | Comment
+ +------+----------------+------------------------------------------------------------
+ | 0 | KEY1 | Keyboard output scan
+ | 1 | KEY2 | Keyboard output scan
+ | 2 | KEY3 | Keyboard output scan
+ | 3 | KEY4 | Keyboard output scan
+ | 4 | KEY5 | Keyboard output scan
+ | 5 | KEY6 | Keyboard output scan
+ | 6 | KEY7 | Keyboard output scan
+ | 7 | BT_WAKE | Bluetooth wake up
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
Chip selects:
+------+----------------+------------------------------------------------------------
| CS1 | CS_FLASH | NAND flash
| CS2 | CS_DSP | DSP
| CS3 | DCS_DRAM | DRAM
+ | CS4 | CS_FLASH2 | (V2) 2nd flash
+------+----------------+------------------------------------------------------------
+ ----------------------------------------------------------------------------------------------
+
Interrupts:
+------+----------------+------------------------------------------------------------
| IRQ7 | IRQ_MAX | MAX 3100 interrupt
+------+----------------+------------------------------------------------------------
+ ----------------------------------------------------------------------------------------------
+
Interrupts on PCMCIA pins:
+------+----------------+------------------------------------------------------------
| IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
| IP_A2| RMII1_MDINT | PHY interrupt for #1
| IP_A3| RMII2_MDINT | PHY interrupt for #2
+ | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
+ | IP_A6| OK_ETH | (V2) Cisco inline power OK
+------+----------------+------------------------------------------------------------
*************************************************************************************************/
/*************************************************************************************************/
+#define CONFIG_CRC32_VERIFY 1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
+
+/*************************************************************************************************/
#endif /* __CONFIG_H */
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