#define CONFIG_SYS_IMMR 0xE0000000
#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_HARD_I2C
#define CONFIG_TSEC_ENET
#define CONFIG_SYS_MEMTEST_END (70<<20)
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDRCDR 0x22000001
+#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \
+ | DDRCDR_NZ_HIZ \
+ | DDRCDR_Q_DRN)
+ /* 0x22000001 */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDR_SIZE 512
#define CONFIG_SYS_FLASH_BASE 0xFF800000
#define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_FLASH_SIZE_SHIFT 3
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
+ | BR_PS_16 \
+ | BR_MS_GPCM \
+ | BR_V)
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
| OR_GPCM_XACS \
| OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX \
- | OR_GPCM_EHTR \
+ | OR_GPCM_TRLX_SET \
+ | OR_GPCM_EHTR_SET \
| OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
- | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
+#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
/*
* U-Boot memory configuration
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x2000000
/* DDR */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
/* PCI */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_10 \
+ | BATL_PP_RW \
| BATL_MEMCOHERENCE \
- | \
- BATL_GUARDEDSTORAGE)
+ | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 \
| BATU_BL_256M \
| BATU_VS \
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
- "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
- "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
- "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
- "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
- "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
- "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
- "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
- "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
+ "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
+ "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
+ "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
+ "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
+ "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
+ "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
+ "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
+ "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
"dhcp_client_id=" MV_CI "\0" \
"dhcp_vendor-class-identifier=" MV_VCI "\0" \
""
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2