Merge with /home/sr/git/u-boot/cfi-flash

[oweals/u-boot.git] / include / configs / MPC86xADS.h

diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h
index a6e26067142df1b65d0dbd9faf88dea7bcc40d17..831cc5ecd3258f05138e34bd96dcd57638ee9dc3 100644 (file)
--- a/include/configs/MPC86xADS.h
+++ b/include/configs/MPC86xADS.h
@@ -21,7 +21,7 @@
 #define CONFIG_MPC86xADS        1       /* new ADS */
 #define CONFIG_FADS            1       /* We are FADS compatible (more or less) */
 
-/* New MPC86xADS - pick one of these */
+/* CPU type - pick one of these */
 #define CONFIG_MPC866T                 1
 #undef CONFIG_MPC866P
 #undef CONFIG_MPC859T
@@ -33,19 +33,17 @@
 #undef CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE                38400
 
-# define CFG_8XX_FACT          5               /* Multiply by 5        */
-# define CFG_8XX_XIN           10000000        /* 10 MHz in    */
+#define CONFIG_8xx_OSCLK               10000000 /* 10MHz oscillator on EXTCLK  */
+#define CONFIG_8xx_CPUCLK_DEFAULT      50000000
+#define CFG_8xx_CPUCLK_MIN             40000000
+#define CFG_8xx_CPUCLK_MAX             80000000
 
 #define CONFIG_DRAM_50MHZ       1
 #define CONFIG_SDRAM_50MHZ      1
 
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register         14-22
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control
- */
-#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
-
 #include "fads.h"
 
+#define CFG_OR5_PRELIM         0xFFFF8110      /* 64Kbyte address space */
+#define CFG_BR5_PRELIM         (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
+
 #endif /* __CONFIG_H */