Merge branch 'mpc86xx'

[oweals/u-boot.git] / include / configs / MPC8641HPCN.h

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index b0897695a7c4b3d9019dde20dfafb4cedcdf84ce..200a38f3e8969b91a26452c5667ddc231eee89f5 100644 (file)
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -100,6 +100,7 @@
  */
 #define CFG_DDR_SDRAM_BASE     0x00000000      /* DDR is system memory*/
 #define CFG_SDRAM_BASE         CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 
@@ -145,6 +146,8 @@
     #define CFG_DDR_CS5_BNDS   0x00000FFF      /* Not done */
 #endif
 
+#define CFG_ID_EEPROM  1
+#define ID_EEPROM_ADDR 0x57
 
 /*
  * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
@@ -265,7 +268,7 @@
 
 #define OF_CPU         "PowerPC,8641@0"
 #define OF_SOC         "soc8641@f8000000"
-#define OF_TBCLK       (bd->bi_busfreq / 8)
+#define OF_TBCLK       (bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500"
 
 #define CFG_64BIT_VSPRINTF     1
@@ -375,10 +378,9 @@
  * BAT0         2G     Cacheable, non-guarded
  * 0x0000_0000  2G     DDR
  */
-#define CFG_DBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT \
-                       | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
-#define CFG_DBAT0U      ( BATU_BL_2G | BATU_VS | BATU_VP )
-#define CFG_IBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
+#define CFG_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
 #define CFG_IBAT0U      CFG_DBAT0U
 
 /*