Merge branch 'mpc86xx'

[oweals/u-boot.git] / include / configs / MPC8641HPCN.h

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index aaf99c150f7eb071da38b0f13ea0d37c2917876a..200a38f3e8969b91a26452c5667ddc231eee89f5 100644 (file)
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -46,7 +46,8 @@
 
 #define CFG_RESET_ADDRESS    0xfff00100
 
-#undef CONFIG_PCI
+/*#undef CONFIG_PCI*/
+#define CONFIG_PCI
 
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -57,6 +58,13 @@
 #define CONFIG_DDR_ECC                 /* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE          0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS     2
+/* #define CONFIG_DDR_INTERLEAVE               1 */
+#define CACHE_LINE_INTERLEAVING                0x20000000
+#define PAGE_INTERLEAVING              0x21000000
+#define BANK_INTERLEAVING              0x22000000
+#define SUPER_BANK_INTERLEAVING                0x23000000
+
 
 #define CONFIG_ALTIVEC          1
 
@@ -92,6 +100,7 @@
  */
 #define CFG_DDR_SDRAM_BASE     0x00000000      /* DDR is system memory*/
 #define CFG_SDRAM_BASE         CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
 
@@ -99,7 +108,10 @@
     /*
      * Determine DDR configuration from I2C interface.
      */
-    #define SPD_EEPROM_ADDRESS 0x51            /* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS1                0x51            /* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS2                0x52            /* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS3                0x53            /* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS4                0x54            /* DDR DIMM */
 
 #else
     /*
@@ -134,6 +146,8 @@
     #define CFG_DDR_CS5_BNDS   0x00000FFF      /* Not done */
 #endif
 
+#define CFG_ID_EEPROM  1
+#define ID_EEPROM_ADDR 0x57
 
 /*
  * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
@@ -199,8 +213,10 @@
 #undef  CFG_RAMBOOT
 #endif
 
-#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT)
-#undef CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
+#if defined(CFG_RAMBOOT)
+#undef CFG_FLASH_CFI_DRIVER
+#undef CONFIG_SPD_EEPROM
+#define CFG_SDRAM_SIZE 256
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
@@ -252,7 +268,7 @@
 
 #define OF_CPU         "PowerPC,8641@0"
 #define OF_SOC         "soc8641@f8000000"
-#define OF_TBCLK       (bd->bi_busfreq / 8)
+#define OF_TBCLK       (bd->bi_busfreq / 4)
 #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500"
 
 #define CFG_64BIT_VSPRINTF     1
@@ -285,7 +301,13 @@
 #define CFG_PCI1_IO_PHYS       CFG_PCI1_IO_BASE
 #define CFG_PCI1_IO_SIZE       0x1000000       /* 16M */
 
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS      0x00000000
+#define CFG_PCI_MEMORY_PHYS     0x00000000
+#define CFG_PCI_MEMORY_SIZE     0x80000000
+
 /* For RTL8139 */
+#define KSEG1ADDR(x)           ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
 #define _IO_BASE                0x00000000
 
 #define CFG_PCI2_MEM_BASE      0xa0000000
@@ -356,10 +378,9 @@
  * BAT0         2G     Cacheable, non-guarded
  * 0x0000_0000  2G     DDR
  */
-#define CFG_DBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT \
-                       | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
-#define CFG_DBAT0U      ( BATU_BL_2G | BATU_VS | BATU_VP )
-#define CFG_IBAT0L      ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
+#define CFG_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
 #define CFG_IBAT0U      CFG_DBAT0U
 
 /*
@@ -419,10 +440,10 @@
  * BAT6         32M    Cache-inhibited, guarded
  * 0xfe00_0000  32M    FLASH
  */
-#define CFG_DBAT6L      ( CFG_FLASH_BASE | BATL_PP_RW \
+#define CFG_DBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
                        | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT6U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CFG_IBAT6L      (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT6U      ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L      ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CFG_IBAT6U      CFG_DBAT6U
 
 #define CFG_DBAT7L 0x00000000