/*
* Copyright 2007-2011 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier: GPL-2.0
*/
/*
#define __CONFIG_H
/* High Level Configuration Options */
-#define CONFIG_MPC86xx 1 /* MPC86xx */
-#define CONFIG_MPC8610 1 /* MPC8610 specific */
-#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
/* video */
#define CONFIG_FSL_DIU_FB
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
-#define CONFIG_VIDEO
-#define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#endif
*/
#define CONFIG_SYS_SCRATCH_VA 0xc0000000
-#define CONFIG_PCI 1 /* Enable PCI/PCIE*/
-#define CONFIG_PCI1 1 /* PCI controler 1 */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#endif
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_R 1
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
/* DDR Setup */
-#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#endif
-
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
#define CONFIG_SYS_FLASH_BASE2 0xf8000000
#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
-
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-/*
- * Pass open firmware flat tree to kernel
- */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* General PCI
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
-
#if defined(CONFIG_PCI)
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_CMD_NET
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_CMD_REGINFO
#define CONFIG_ULI526X
#ifdef CONFIG_ULI526X
-#define CONFIG_ETHADDR 00:E0:0C:00:00:01
#endif
/************************************************************
************************************************************/
#define CONFIG_PCI_OHCI 1
#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL 1
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
-#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
-
/*
* BAT5 128K Cacheable, non-guarded
* 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
-
/*
* Environment
*/
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_CMD_SAVEENV
-#endif
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SCSI
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_USB
+#define CONFIG_SCSI
#endif
-
#define CONFIG_WATCHDOG /* watchdog enabled */
#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
#define CONFIG_NETMASK 255.255.255.0
/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
+#define CONFIG_LOADADDR 0x10000000
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-#define CONFIG_BAUDRATE 115200
-
#if defined(CONFIG_PCI1)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
#ifdef ENV_DEBUG
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
- "bdev=sda3\0" \
- "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
- "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
- "maxcpus=1" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
- "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=0x18000000\0" \
+"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
+"fdtaddr=0x17c00000\0" \
+"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
+"bdev=sda3\0" \
+"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+"maxcpus=1" \
+"eoi=mw e00400b0 0\0" \
+"iack=md e00400a0 1\0" \
+"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
"md ${a}f00 5\0" \
- "ddr1regs=setenv a e0002; run ddrreg\0" \
- "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
+"ddr1regs=setenv a e0002; run ddrreg\0" \
+"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
"md ${a}e60 1; md ${a}ef0 1d\0" \
- "guregs=setenv a e00e0; run gureg\0" \
- "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
- "mcmregs=setenv a e0001; run mcmreg\0" \
- "diuregs=md e002c000 1d\0" \
- "dium=mw e002c01c\0" \
- "diuerr=md e002c014 1\0" \
- "pmregs=md e00e1000 2b\0" \
- "lawregs=md e0000c08 4b\0" \
- "lbcregs=md e0005000 36\0" \
- "dma0regs=md e0021100 12\0" \
- "dma1regs=md e0021180 12\0" \
- "dma2regs=md e0021200 12\0" \
- "dma3regs=md e0021280 12\0" \
+"guregs=setenv a e00e0; run gureg\0" \
+"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
+"mcmregs=setenv a e0001; run mcmreg\0" \
+"diuregs=md e002c000 1d\0" \
+"dium=mw e002c01c\0" \
+"diuerr=md e002c014 1\0" \
+"pmregs=md e00e1000 2b\0" \
+"lawregs=md e0000c08 4b\0" \
+"lbcregs=md e0005000 36\0" \
+"dma0regs=md e0021100 12\0" \
+"dma1regs=md e0021180 12\0" \
+"dma2regs=md e0021200 12\0" \
+"dma3regs=md e0021280 12\0" \
PCI_ENV \
PCIE_ENV \
DMA_ENV
#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
- "bdev=sda3\0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=0x18000000\0" \
+ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
+ "fdtaddr=0x17c00000\0" \
+ "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
+ "bdev=sda3\0"
#endif
#define CONFIG_NFSBOOTCOMMAND \
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