projects / oweals / u-boot.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
new at91_emac network driver (NET_MULTI api)
[oweals/u-boot.git] / include / configs / MPC8569MDS.h
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 6e8f1ff6067deabbe312932203b0aea4b9268672..4f4bcbeda85b2f8334e1f9d157d1d3d1b5de254d 100644 (file)
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -44,13 +44,6 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the MDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif
@@ -58,6 +51,11 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CLK_FREQ    66666666
 #define CONFIG_DDR_CLK_FREQ    CONFIG_SYS_CLK_FREQ
 
+#ifdef CONFIG_MK_ATM
+#define CONFIG_PQ_MDS_PIB
+#define CONFIG_PQ_MDS_PIB_ATM
+#endif
+
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
@@ -70,6 +68,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_ENABLE_36BIT_PHYS       1
 
 #define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init */
+#define CONFIG_HWCONFIG
 
 #define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END         0x00400000
@@ -180,6 +179,29 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
+/* Chip select 3 - NAND */
+#define CONFIG_SYS_NAND_BASE           0xFC000000
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_MTD_NAND_VERIFY_WRITE   1
+#define CONFIG_CMD_NAND                        1
+#define CONFIG_NAND_FSL_ELBC           1
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+#define CONFIG_NAND_BR_PRELIM  (CONFIG_SYS_NAND_BASE_PHYS \
+                               | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+                               | BR_PS_8            /* Port Size = 8 bit */ \
+                               | BR_MS_FCM          /* MSEL = FCM */ \
+                               | BR_V)              /* valid */
+#define CONFIG_NAND_OR_PRELIM  (0xFFFC0000          /* length 256K */ \
+                               | OR_FCM_CSCT \
+                               | OR_FCM_CST \
+                               | OR_FCM_CHT \
+                               | OR_FCM_SCY_1 \
+                               | OR_FCM_TRLX \
+                               | OR_FCM_EHTR)
+#define CONFIG_SYS_BR3_PRELIM  CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR3_PRELIM  CONFIG_NAND_OR_PRELIM /* NAND Options */
 
 /*
  * SDRAM on the LocalBus
@@ -206,6 +228,7 @@ extern unsigned long get_clock_freq(void);
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX              1
+#define CONFIG_SERIAL_MULTI            1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
@@ -229,9 +252,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP          1
 #define CONFIG_OF_STDOUT_VIA_ALIAS     1
 
-#define CONFIG_SYS_64BIT_VSPRINTF      1
-#define CONFIG_SYS_64BIT_STRTOUL       1
-
 /*
  * I2C
  */
@@ -258,8 +278,14 @@ extern unsigned long get_clock_freq(void);
 
 #define PLPPAR1_I2C_BIT_MASK           0x0000000F
 #define PLPPAR1_I2C2_VAL               0x00000000
+#define PLPPAR1_ESDHC_VAL              0x0000000A
 #define PLPDIR1_I2C_BIT_MASK           0x0000000F
 #define PLPDIR1_I2C2_VAL               0x0000000F
+#define PLPDIR1_ESDHC_VAL              0x00000006
+#define PLPPAR1_UART0_BIT_MASK         0x00000fc0
+#define PLPPAR1_ESDHC_4BITS_VAL                0x00000a80
+#define PLPDIR1_UART0_BIT_MASK         0x00000fc0
+#define PLPDIR1_ESDHC_4BITS_VAL                0x00000a80
 
 /*
  * General PCI
@@ -300,12 +326,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       7
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16        /* CLK16 for RMII */
 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       8       /* 0x8 for RMII */
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH1 */
 
@@ -319,12 +347,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       1
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16        /* CLK 16 for RMII */
 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9     /* 0x9 for RMII */
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH2 */
 
@@ -338,12 +368,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC3_PHY_ADDR       2
-#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK16 /* CLK_16 for RMII */
 #define CONFIG_SYS_UEC3_ETH_TYPE       FAST_ETH
 #define CONFIG_SYS_UEC3_PHY_ADDR       0xA     /* 0xA for RMII */
-#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH3 */
 
@@ -357,12 +389,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC4_PHY_ADDR       3
-#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK16 /* CLK16 for RMII */
 #define CONFIG_SYS_UEC4_ETH_TYPE       FAST_ETH
 #define CONFIG_SYS_UEC4_PHY_ADDR       0xB     /* 0xB for RMII */
-#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH4 */
 
@@ -375,7 +409,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC6_PHY_ADDR       4
-#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII
+#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII
+#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
 #endif /* CONFIG_UEC_ETH6 */
 
 #undef CONFIG_UEC_ETH8         /* GETH8 */
@@ -387,7 +422,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC8_PHY_ADDR       6
-#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII
+#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII
+#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
 #endif /* CONFIG_UEC_ETH8 */
 
 #endif /* CONFIG_QE */
@@ -450,6 +486,18 @@ extern unsigned long get_clock_freq(void);
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled */
 
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /*
  * Miscellaneous configurable options
  */
Unnamed repository; edit this file 'description' to name the repository.