Fix numerous bugs in the 8568 UEC support

[oweals/u-boot.git] / include / configs / MPC8568MDS.h

diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index eef168c252d469d8b1efc31f2ccb9e6aa8aad702..80ccda51f7c781d458d410964d68183ae2844a88 100644 (file)
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -28,20 +28,21 @@
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE           1       /* BOOKE */
-#define CONFIG_E500                    1       /* BOOKE e500 family */
+#define CONFIG_E500            1       /* BOOKE e500 family */
 #define CONFIG_MPC85xx         1       /* MPC8540/60/55/41/48/68 */
 #define CONFIG_MPC8568         1       /* MPC8568 specific */
 #define CONFIG_MPC8568MDS      1       /* MPC8568MDS board specific */
 
-#undef CONFIG_PCI
+#define CONFIG_PCI
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
+#define CONFIG_QE                      /* Enable QE */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL                 /* possible DLL fix needed */
 /*#define CONFIG_DDR_2T_TIMING          Sets the 2T timing bit */
 
 /*#define CONFIG_DDR_ECC*/                     /* only for ECC DDR module */
-/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/  /*       DDR controller or DMA? */
+/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/  /* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE          0xDeadBeef
 
 
@@ -297,6 +298,7 @@ extern unsigned long get_clock_freq(void);
 
 #define OF_CPU                 "PowerPC,8568@0"
 #define OF_SOC                 "soc8568@e0000000"
+#define OF_QE                  "qe@e0080000"
 #define OF_TBCLK               (bd->bi_busfreq / 8)
 #define OF_STDOUT_PATH         "/soc8568@e0000000/serial@4600"
 
@@ -306,11 +308,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
 #define CONFIG_HARD_I2C                /* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
 #define CFG_I2C_SPEED          400000  /* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR    0x57
+#define CFG_I2C_EEPROM_ADDR    0x52
 #define CFG_I2C_SLAVE          0x7F
-#define CFG_I2C_NOPROBES        {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES        {{0,0x69}}     /* Don't probe these addrs */
 #define CFG_I2C_OFFSET         0x3000
+#define CFG_I2C2_OFFSET                0x3100
 
 /*
  * General PCI
@@ -318,7 +323,7 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_PCI1_MEM_BASE      0x80000000
 #define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE      0x10000000      /* 256M */
+#define CFG_PCI1_MEM_SIZE      0x20000000      /* 512M */
 #define CFG_PCI1_IO_BASE       0x00000000
 #define CFG_PCI1_IO_PHYS       0xe2000000
 #define CFG_PCI1_IO_SIZE       0x00800000      /* 8M */
@@ -337,6 +342,44 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play */
 
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#ifndef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME         "FSL UEC0"
+#endif
+#define CONFIG_PHY_MODE_NEED_CHANGE
+#define CONFIG_eTSEC_MDIO_BUS
+
+#ifdef CONFIG_eTSEC_MDIO_BUS
+#define CONFIG_MIIM_ADDRESS    0xE0024520
+#endif
+
+#define CONFIG_UEC_ETH1         /* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM        0       /* UCC1 */
+#define CFG_UEC1_RX_CLK         QE_CLK_NONE
+#define CFG_UEC1_TX_CLK         QE_CLK16
+#define CFG_UEC1_ETH_TYPE       GIGA_ETH
+#define CFG_UEC1_PHY_ADDR       7
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#endif
+
+#define CONFIG_UEC_ETH2         /* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM        1       /* UCC2 */
+#define CFG_UEC2_RX_CLK         QE_CLK_NONE
+#define CFG_UEC2_TX_CLK         QE_CLK16
+#define CFG_UEC2_ETH_TYPE       GIGA_ETH
+#define CFG_UEC2_PHY_ADDR       1
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#endif
+#endif /* CONFIG_QE */
+
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
@@ -345,21 +388,17 @@ extern unsigned long get_clock_freq(void);
 
 #endif /* CONFIG_PCI */
 
-
-#if defined(CONFIG_TSEC_ENET)
-
 #ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI       1
 #endif
 
+#if defined(CONFIG_TSEC_ENET)
+
 #define CONFIG_MII             1       /* MII PHY management */
 #define CONFIG_TSEC1   1
 #define CONFIG_TSEC1_NAME      "eTSEC0"
 #define CONFIG_TSEC2   1
 #define CONFIG_TSEC2_NAME      "eTSEC1"
-#undef  CONFIG_TSEC3
-#undef  CONFIG_TSEC4
-#undef  CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR         2
 #define TSEC2_PHY_ADDR         3
@@ -367,7 +406,10 @@ extern unsigned long get_clock_freq(void);
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
 
-/* Options are: eTSEC[0-3] */
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC2_FLAGS            TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
 #define CONFIG_ETHPRIME                "eTSEC0"
 
 #endif /* CONFIG_TSEC_ENET */
@@ -457,12 +499,15 @@ extern unsigned long get_clock_freq(void);
  */
 
 /* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 #define CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 #define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 #endif
 
 #define CONFIG_IPADDR    192.168.1.253