+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright 2020 NXP
*/
/*
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xfff80000
-#endif
-
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/*
* I2C
*/
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
+#else
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
+#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
+#endif
+#define CONFIG_SYS_I2C_FSL
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_NAME "Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
/*
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1
+#define CONFIG_SYS_PCIE1_NAME "Slot"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
+
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
-#define CONFIG_PHY_MARVELL
-
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
/*
* Environment
*/
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
-#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
/*
* For booting Linux, the board info and command line data
#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
projects / oweals / u-boot.git / blobdiff