SX1: Fix second flash mapping

[oweals/u-boot.git] / include / configs / MPC8544DS.h

diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index c47374acb6a1790f8736fa04c1c456f6f3e549da..59cfde6284b047f6a79d2c7e8238dc7761b0a556 100644 (file)
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -66,7 +66,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache */
 #define CONFIG_BTB                     /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING          /* toggle addr streaming */
 
 /*
  * Only possible on E500 Version 2 or newer cores.
@@ -97,7 +96,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
@@ -207,8 +206,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VCFGEN1_MASK     (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 
 
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK      1
 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_END       0x00004000      /* End of used area in RAM */
@@ -266,55 +263,61 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
+#define CONFIG_SYS_PCIE_VIRT           0x80000000      /* 1G PCIE TLB */
 #define CONFIG_SYS_PCIE_PHYS           0x80000000      /* 1G PCIE TLB */
+#define CONFIG_SYS_PCI_VIRT            0xc0000000      /* 512M PCI TLB */
 #define CONFIG_SYS_PCI_PHYS            0xc0000000      /* 512M PCI TLB */
 
-#define CONFIG_SYS_PCI1_MEM_BASE       0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BUS        0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       0xc0000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe1000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00010000      /* 64k */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE     0x80000000
-
 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE      0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_VIRT      0x80000000
+#define CONFIG_SYS_PCIE2_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0x80000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xe1010000
+#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe1010000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE      0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xe1020000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe1020000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_MEM_BASE      0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      CONFIG_SYS_PCIE3_MEM_BASE
+#define CONFIG_SYS_PCIE3_MEM_VIRT      0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS       0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS      0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x00100000      /* 1M */
-#define CONFIG_SYS_PCIE3_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE3_IO_VIRT       0xb0100000      /* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xb0100000      /* reuse mem LAW */
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00100000      /* 1M */
-#define CONFIG_SYS_PCIE3_MEM_BASE2     0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2     CONFIG_SYS_PCIE3_MEM_BASE2
+#define CONFIG_SYS_PCIE3_MEM_VIRT2     0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_BUS2      0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_PHYS2     0xb0200000
 #define CONFIG_SYS_PCIE3_MEM_SIZE2     0x00200000      /* 1M */
 
 #if defined(CONFIG_PCI)
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE2_IO_PHYS
+#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE2_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCI1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
@@ -344,8 +347,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 #ifndef CONFIG_PCI_PNP
-       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
-       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BASE
+       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
+       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
        #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 #endif