SX1: Fix second flash mapping

[oweals/u-boot.git] / include / configs / MPC8544DS.h

diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 8d0d7848d189dc951695c9a9084c92b6f9d433ff..59cfde6284b047f6a79d2c7e8238dc7761b0a556 100644 (file)
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -263,50 +263,61 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
+#define CONFIG_SYS_PCIE_VIRT           0x80000000      /* 1G PCIE TLB */
 #define CONFIG_SYS_PCIE_PHYS           0x80000000      /* 1G PCIE TLB */
+#define CONFIG_SYS_PCI_VIRT            0xc0000000      /* 512M PCI TLB */
 #define CONFIG_SYS_PCI_PHYS            0xc0000000      /* 512M PCI TLB */
 
+#define CONFIG_SYS_PCI1_MEM_VIRT       0xc0000000
 #define CONFIG_SYS_PCI1_MEM_BUS        0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_PHYS       0xc0000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe1000000
 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00010000      /* 64k */
 
 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT      0x80000000
 #define CONFIG_SYS_PCIE2_MEM_BUS       0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0x80000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xe1010000
 #define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe1010000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 1, Slot 2,tgtid 2, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xe1020000
 #define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe1020000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 3, direct to uli, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT      0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      CONFIG_SYS_PCIE3_MEM_BUS
+#define CONFIG_SYS_PCIE3_MEM_PHYS      0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x00100000      /* 1M */
+#define CONFIG_SYS_PCIE3_IO_VIRT       0xb0100000      /* reuse mem LAW */
 #define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xb0100000      /* reuse mem LAW */
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00100000      /* 1M */
+#define CONFIG_SYS_PCIE3_MEM_VIRT2     0xb0200000
 #define CONFIG_SYS_PCIE3_MEM_BUS2      0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2     CONFIG_SYS_PCIE3_MEM_BUS2
+#define CONFIG_SYS_PCIE3_MEM_PHYS2     0xb0200000
 #define CONFIG_SYS_PCIE3_MEM_SIZE2     0x00200000      /* 1M */
 
 #if defined(CONFIG_PCI)
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE2_IO_PHYS
+#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE2_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCI1_IO_PHYS*/
+/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCI1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO