8xxx: Second UART port added for MPC85xx, MPC83xx, MPC86xx processors

[oweals/u-boot.git] / include / configs / MPC8541CDS.h

diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 399189c598e081016a9628782cb7cb000c8e90e6..813512c045a2ca23cf28235caab9246012a0f1ad 100644 (file)
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -206,42 +206,19 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_LBC_LSRT            0x20000000  /* LB sdram refresh timer */
 #define CONFIG_SYS_LBC_MRTPR           0x00000000  /* LB refresh timer prescal*/
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN      (1 << (31 -  1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516  (3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617  (4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16    (7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7  (7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6  (6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8       (1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4      (0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3       (3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
-
 /*
  * Common settings for all Local Bus SDRAM commands.
  * At run time, either BSMA1516 (for CPU 1.1)
  *                  or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON    ( CONFIG_SYS_LBC_LSDMR_RFCR16           \
-                               | CONFIG_SYS_LBC_LSDMR_PRETOACT7        \
-                               | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \
-                               | CONFIG_SYS_LBC_LSDMR_BL8              \
-                               | CONFIG_SYS_LBC_LSDMR_WRC4             \
-                               | CONFIG_SYS_LBC_LSDMR_CL3              \
-                               | CONFIG_SYS_LBC_LSDMR_RFEN             \
+#define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFCR16          \
+                               | LSDMR_PRETOACT7       \
+                               | LSDMR_ACTTORW7        \
+                               | LSDMR_BL8             \
+                               | LSDMR_WRC4            \
+                               | LSDMR_CL3             \
+                               | LSDMR_RFEN            \
                                )
 
 /*
@@ -341,17 +318,21 @@ extern unsigned long get_clock_freq(void);
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT       0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
 
-#define CONFIG_SYS_PCI2_MEM_BASE       0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_VIRT       0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS       0xa0000000
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI2_IO_VIRT        0xe2100000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2100000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x100000        /* 1M */