Merge branch 'mpc86xx'

[oweals/u-boot.git] / include / configs / MPC8540ADS.h

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 533b58796650516ddef9cc1ba69176ffff83666f..8e4d2c95a44eb763d7d838a9e64bc57241ed9d48 100644 (file)
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -49,10 +49,12 @@
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_ECC                 /* only for ECC DDR module */
 #define CONFIG_DDR_DLL                 /* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING           /* Sets the 2T timing bit */
 
+#define CONFIG_DDR_ECC                 /* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE          0xDeadBeef
+
 
 /*
  * sysclk for MPC85xx
@@ -66,6 +68,10 @@
  * The board, however, can run at 66MHz.  In any event, this value
  * must match the settings of some switches.  Details can be found
  * in the README.mpc85xxads.
+ *
+ * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
+ * 33MHz to accommodate, based on a PCI pin.
+ * Note that PCI-X won't work at 33MHz.
  */
 
 #ifndef CONFIG_SYS_CLK_FREQ
@@ -291,6 +297,21 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE    1
+#define CONFIG_OF_BOARD_SETUP  1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE  8192
+
+#define OF_CPU                 "PowerPC,8540@0"
+#define OF_SOC                 "soc8540@e0000000"
+#define OF_TBCLK               (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH         "/soc8540@e0000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF     1
+#define CFG_64BIT_STRTOUL      1
+
 /* I2C */
 #define  CONFIG_HARD_I2C               /* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
@@ -310,9 +331,10 @@
 #define CFG_PCI1_MEM_BASE      0x80000000
 #define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE
 #define CFG_PCI1_MEM_SIZE      0x20000000      /* 512M */
-#define CFG_PCI1_IO_BASE       0xe2000000
-#define CFG_PCI1_IO_PHYS       CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE       0x1000000       /* 16M */
+
+#define CFG_PCI1_IO_BASE       0x0
+#define CFG_PCI1_IO_PHYS       0xe2000000
+#define CFG_PCI1_IO_SIZE       0x100000        /* 1M */
 
 #if defined(CONFIG_PCI)
 
@@ -342,7 +364,9 @@
 
 #define CONFIG_MII             1       /* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1   1
+#define CONFIG_MPC85XX_TSEC1_NAME      "TSEC0"
 #define CONFIG_MPC85XX_TSEC2   1
+#define CONFIG_MPC85XX_TSEC2_NAME      "TSEC1"
 #define TSEC1_PHY_ADDR         0
 #define TSEC2_PHY_ADDR         1
 #define TSEC1_PHYIDX           0
@@ -351,11 +375,13 @@
 
 #if CONFIG_HAS_FEC
 #define CONFIG_MPC85XX_FEC     1
+#define CONFIG_MPC85XX_FEC_NAME                "FEC"
 #define FEC_PHY_ADDR           3
 #define FEC_PHYIDX             0
 #endif
 
-#define CONFIG_ETHPRIME                "MOTO ENET0"
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME                "TSEC0"
 
 #endif /* CONFIG_TSEC_ENET */