Merge branch 'master' of git://git.denx.de/u-boot-mips

[oweals/u-boot.git] / include / configs / MPC8540ADS.h

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5a14969a6c39f69703b9bddf18d93259438de11b..0d03b0b85f8595d4b6a1ce324560bba435d31317 100644 (file)
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -46,6 +46,7 @@
 #endif
 
 #define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
@@ -78,7 +79,6 @@
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache */
 #define CONFIG_BTB                     /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING          /* toggle addr streaming */
 
 #define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest region */
 #define CONFIG_SYS_MEMTEST_END         0x00400000
@@ -257,7 +257,6 @@
 #define CONFIG_SYS_OR4_PRELIM          0xffffe1f1
 #define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */
@@ -309,18 +308,21 @@
 #define CONFIG_SYS_I2C_OFFSET          0x3000
 
 /* RapidIO MMU */
-#define CONFIG_SYS_RIO_MEM_BASE        0xc0000000      /* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS        CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_VIRT        0xc0000000      /* base address */
+#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000      /* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS        0xc0000000
 #define CONFIG_SYS_RIO_MEM_SIZE        0x20000000      /* 128M */
 
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT       0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */