pxa: fixing get_timer to return time in miliseconds.

[oweals/u-boot.git] / include / configs / MPC8536DS.h

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 63a0f7e675c4558c7308c0bc1ef4cae55fc51d53..bbb448d55fdf9572092e57da5648750c69c1a96c 100644 (file)
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -34,6 +34,7 @@
 #define CONFIG_MPC8536         1
 #define CONFIG_MPC8536DS       1
 
+#define CONFIG_FSL_ELBC                1       /* Has Enhanced localbus controller */
 #define CONFIG_PCI             1       /* Enable PCI/PCIE */
 #define CONFIG_PCI1            1       /* Enable PCI controller 1 */
 #define CONFIG_PCIE1           1       /* PCIE controler 1 (slot 1) */
@@ -71,6 +72,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_L2_CACHE                        /* toggle L2 cache */
 #define CONFIG_BTB                     /* toggle branch predition */
 
+#define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init */
+
 #define CONFIG_ENABLE_36BIT_PHYS       1
 
 #define CONFIG_SYS_MEMTEST_START       0x00000000      /* memtest works on */
@@ -256,7 +259,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
 
 /* NAND flash config */
-#define CONFIG_NAND_BR_PRELIM  (CONFIG_SYS_NAND_BASE_PHYS \
+#define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8              /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
@@ -273,20 +276,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 
-#define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8              /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V)                 /* valid */
 #define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8              /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V)                 /* valid */
 #define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
 
-#define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8              /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
@@ -527,6 +530,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled */
 
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /*
  * Miscellaneous configurable options
  */