/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
* Addresses are mapped 1-1.
*/
#define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI 1
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 2
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 4
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif
/*
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
-#define CONFIG_ETHADDR 00:04:9f:ef:01:01
-#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
-#define CONFIG_ETH2ADDR 00:04:9f:ef:01:03
-#define CONFIG_ETH3ADDR 00:04:9f:ef:01:04
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_HOSTNAME mpc8360erdk
#define CONFIG_BOOTFILE uImage
-#define CONFIG_IPADDR 10.0.0.99
-#define CONFIG_SERVERIP 10.0.0.2
-#define CONFIG_GATEWAYIP 10.0.0.2
-#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_ROOTPATH /nfsroot/
#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
"consoledev=ttyS0\0"\
"loadaddr=a00000\0"\
"fdtaddr=900000\0"\
- "fdtfile=dtb\0"\
+ "fdtfile=mpc836x_rdk.dtb\0"\
"fsfile=fs\0"\
"ubootfile=u-boot.bin\0"\
"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\