ColdFire: Add M5253DEMO platform support for MCF5253

[oweals/u-boot.git] / include / configs / MPC8360ERDK.h

diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 7b7d6f50c00b59b8ec3abbf437989bd2db52f5ba..6898495b8db17e71e382615857a5303210c1abe9 100644 (file)
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -184,7 +184,7 @@
  * FLASH on the Local Bus
  */
 #define CFG_FLASH_CFI          /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER   /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER        /* use the CFI driver */
 #define CFG_FLASH_SIZE         8 /* max FLASH size is 32M */
 #define CFG_FLASH_PROTECTION   1 /* Use intel Flash protection. */
 
@@ -195,7 +195,7 @@
                        (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
                        BR_V)   /* valid */
 #define CFG_OR0_PRELIM         ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_XACS | OR_GPCM_SCY_15 | \
                                OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 
@@ -419,6 +419,8 @@
  * MMU Setup
  */
 
+#define CONFIG_HIGH_BATS       1       /* High BATs supported */
+
 /* DDR: cache cacheable */
 #define CFG_IBAT0L     (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U     (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)