Merge with /home/mk/11-cmb1920/u-boot#4upstream

[oweals/u-boot.git] / include / configs / MPC8349EMDS.h

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index e68c41accf5c5dd5ab0668dda1484bf7a4f28ef5..5bed2d0a29fa05b37f276ce58574c48ecc661d99 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -73,7 +73,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F              /* call board_pre_init */
 
-#define CFG_IMMRBAR            0xE0000000
+#define CFG_IMMR               0xE0000000
 
 #undef CFG_DRAM_TEST                           /* memory test, takes time */
 #define CFG_MEMTEST_START      0x00000000      /* memtest region */
@@ -311,8 +311,8 @@
 #define CFG_BAUDRATE_TABLE  \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_IMMRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_IMMRBAR+0x4600)
+#define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
@@ -335,6 +335,7 @@
 /* I2C */
 #define CONFIG_HARD_I2C                        /* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
+#define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
 #define CFG_I2C_SPEED          400000  /* I2C speed and slave address */
@@ -345,9 +346,9 @@
 
 /* TSEC */
 #define CFG_TSEC1_OFFSET 0x24000
-#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
 #define CFG_TSEC2_OFFSET 0x25000
-#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
 
 /* USB */
 #define CFG_USE_MPC834XSYS_USB_PHY     1 /* Use SYS board PHY */
@@ -641,8 +642,8 @@
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CFG_IBAT5L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U     (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L     (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U     (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CFG_IBAT6L     (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)