mpc83xx: Simplify BR,OR lines

[oweals/u-boot.git] / include / configs / MPC8349EMDS.h

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index fa73b81c3a0b96f4fb98bf1e8509d149c39b3c00..4cda1589b676f09673fe52c2ddc75353af49c428 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -123,19 +123,9 @@
 #define CONFIG_SYS_FLASH_BASE          0xFE000000      /* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE          32      /* max flash size in MB */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port  */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      256     /* max sectors per device */
@@ -157,18 +147,10 @@
  */
 #define CONFIG_SYS_BCSR                        0xE2400000
                                        /* Access window base at BCSR base */
-#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_BCSR \
-                                       | BR_PS_8 \
-                                       | BR_MS_GPCM \
-                                       | BR_V)
-                                       /* 0x00000801 */
-#define CONFIG_SYS_OR1_PRELIM          (OR_AM_32KB \
-                                       | OR_GPCM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_CLEAR \
-                                       | OR_GPCM_EHTR_CLEAR)
-                                       /* 0xFFFFE8F0 */
+
+/* BCSR */
+#define CONFIG_SYS_BR1_PRELIM          (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM          (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000      /* Initial RAM addr */