Merge tag 'efi-2020-01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

[oweals/u-boot.git] / include / configs / MPC832XEMDS.h

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index d51d5ce06d5b30139870abe133864fb676d0918f..26a44071efd51242c5ec7187397747e5181541c6 100644 (file)
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -10,24 +10,16 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300            1       /* E300 family */
-#define CONFIG_QE              1       /* Has QE */
 
 /*
  * System IO Config
  */
 #define CONFIG_SYS_SICRL               0x00000000
 
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR                0xE0000000
-
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE    0x00000000      /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory */
 #define CONFIG_SYS_DDRCDR      0x73000002      /* DDR II voltage is 1.8V */
 
 #undef CONFIG_SPD_EEPROM
@@ -120,33 +112,12 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP           LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV         LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR            0x00000000
-
 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_BASE  0xFE000000      /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE  16      /* FLASH size is 16M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-                               | OR_GPCM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xfe006ff7 */
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      128     /* sectors per device */
@@ -159,19 +130,6 @@
 #define CONFIG_SYS_BCSR                        0xF8000000
                                        /* Access window base at BCSR base */
 
-#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_BCSR \
-                                       | BR_PS_8 \
-                                       | BR_MS_GPCM \
-                                       | BR_V)
-#define CONFIG_SYS_OR1_PRELIM          (OR_AM_32KB \
-                                       | OR_GPCM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFFE9F7 */
 
 /*
  * Windows to access PIB via local bus
@@ -183,39 +141,12 @@
 /*
  * CS2 on Local Bus, to PIB
  */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_PIB_BASE \
-                               | BR_PS_8 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-                               /* 0xF8008801 */
-#define CONFIG_SYS_OR2_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
-                               | OR_GPCM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xffffe9f7 */
+
 
 /*
  * CS3 on Local Bus, to PIB
  */
-#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_PIB_BASE + \
-                                       CONFIG_SYS_PIB_WINDOW_SIZE) \
-                               | BR_PS_8 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-                               /* 0xF8010801 */
-#define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
-                               | OR_GPCM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xffffe9f7 */
+
 
 /*
  * Serial Port
@@ -344,14 +275,6 @@
 #define CONFIG_SYS_BOOTMAPSZ           (256 << 20)
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
-                                HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2                HID2_HBE
-
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE   230400  /* speed of kgdb serial port */
 #endif