mpc83xx: Normalize BR/OR option lines
[oweals/u-boot.git] / include / configs / MPC8323ERDB.h
index 578202f3be3f669111782117bc13af082707ca38..30f1e4453d167f83534733db92302cfda32cc265 100644 (file)
  */
 #define CONFIG_E300            1       /* E300 family */
 #define CONFIG_QE              1       /* Has QE */
-#define CONFIG_MPC832x         1       /* MPC832x CPU specific */
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN      66666667        /* in Hz */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ    CONFIG_83XX_CLKIN
-#endif
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-       HRCWL_DDR_TO_SCB_CLK_2X1 |\
-       HRCWL_VCO_1X2 |\
-       HRCWL_CSB_TO_CLKIN_2X1 |\
-       HRCWL_CORE_TO_CSB_2_5X1 |\
-       HRCWL_CE_PLL_VCO_DIV_2 |\
-       HRCWL_CE_PLL_DIV_1X1 |\
-       HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-       HRCWH_PCI_HOST |\
-       HRCWH_PCI1_ARBITER_ENABLE |\
-       HRCWH_CORE_ENABLE |\
-       HRCWH_FROM_0X00000100 |\
-       HRCWH_BOOTSEQ_DISABLE |\
-       HRCWH_SW_WATCHDOG_DISABLE |\
-       HRCWH_ROM_LOC_LOCAL_16BIT |\
-       HRCWH_BIG_ENDIAN |\
-       HRCWH_LALE_NORMAL)
 
 /*
  * System IO Config
 #define CONFIG_SYS_FLASH_BASE  0xFE000000      /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          16      /* FLASH size is 16M */
 
-                                       /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_32MB)
 
 #define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB \
                                | OR_GPCM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                 HID0_ENABLE_INSTRUCTION_CACHE)
 #define CONFIG_SYS_HID2                HID2_HBE
 
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS       1       /* High BATs supported */
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE \
-                               | BATL_PP_RW \
-                               | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE \
-                               | BATU_BL_256M \
-                               | BATU_VS \
-                               | BATU_VP)
-#define CONFIG_SYS_DBAT0L      CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
-
-/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_IMMR \
-                               | BATL_PP_RW \
-                               | BATL_CACHEINHIBIT \
-                               | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT1U      (CONFIG_SYS_IMMR \
-                               | BATU_BL_4M \
-                               | BATU_VS \
-                               | BATU_VP)
-#define CONFIG_SYS_DBAT1L      CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U      CONFIG_SYS_IBAT1U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_FLASH_BASE \
-                               | BATL_PP_RW \
-                               | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U      (CONFIG_SYS_FLASH_BASE \
-                               | BATU_BL_32M \
-                               | BATU_VS \
-                               | BATU_VP)
-#define CONFIG_SYS_DBAT2L      (CONFIG_SYS_FLASH_BASE \
-                               | BATL_PP_RW \
-                               | BATL_CACHEINHIBIT \
-                               | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
-
-#define CONFIG_SYS_IBAT3L      (0)
-#define CONFIG_SYS_IBAT3U      (0)
-#define CONFIG_SYS_DBAT3L      CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT4U      (CONFIG_SYS_INIT_RAM_ADDR \
-                               | BATU_BL_128K \
-                               | BATU_VS \
-                               | BATU_VP)
-#define CONFIG_SYS_DBAT4L      CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U      CONFIG_SYS_IBAT4U
-
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_PCI1_MEM_PHYS \
-                               | BATL_PP_RW \
-                               | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_PCI1_MEM_PHYS \
-                               | BATU_BL_256M \
-                               | BATU_VS \
-                               | BATU_VP)
-#define CONFIG_SYS_DBAT5L      CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PCI1_MMIO_PHYS \
-                               | BATL_PP_RW \
-                               | BATL_CACHEINHIBIT \
-                               | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PCI1_MMIO_PHYS \
-                               | BATU_BL_256M \
-                               | BATU_VS \
-                               | BATU_VP)
-#define CONFIG_SYS_DBAT6L      CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
-#else
-#define CONFIG_SYS_IBAT5L      (0)
-#define CONFIG_SYS_IBAT5U      (0)
-#define CONFIG_SYS_IBAT6L      (0)
-#define CONFIG_SYS_IBAT6U      (0)
-#define CONFIG_SYS_DBAT5L      CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L      CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
-#endif
-
-/* Nothing in BAT7 */
-#define CONFIG_SYS_IBAT7L      (0)
-#define CONFIG_SYS_IBAT7U      (0)
-#define CONFIG_SYS_DBAT7L      CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U      CONFIG_SYS_IBAT7U
-
 #if (CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE   230400  /* speed of kgdb serial port */
 #endif