Added initial eNET board support

[oweals/u-boot.git] / include / configs / MPC8315ERDB.h

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 1225270ffbeb938ef478f95b1c793d720869fa32..e4ada652b593a978af1fb5929a5f7234ea52972a 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -118,23 +118,23 @@
                                | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
                                | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
                                /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1        ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
-                               | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
-                               | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+#define CONFIG_SYS_DDR_TIMING_1        ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
+                               | ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+                               | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
                                | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
                                | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
                                | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
                                | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
                                | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
-                               /* 0x39356222 */
+                               /* 0x27256222 */
 #define CONFIG_SYS_DDR_TIMING_2        ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
                                | ( 4 << TIMING_CFG2_CPO_SHIFT ) \
                                | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
                                | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
                                | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
                                | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
-                               | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
-                               /* 0x121048c7 */
+                               | ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+                               /* 0x121048c5 */
 #define CONFIG_SYS_DDR_INTERVAL        ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
                                | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
                                /* 0x03600100 */
@@ -166,7 +166,7 @@
 #undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN         (384 * 1024) /* Reserve 384 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN          (512 * 1024) /* Reserved for malloc */
 
 /*
@@ -223,15 +223,16 @@
  */
 #define CONFIG_SYS_NAND_BASE           0xE0600000      /* 0xE0600000 */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define NAND_MAX_CHIPS         1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_VERIFY_WRITE   1
+#define CONFIG_CMD_NAND                        1
+#define CONFIG_NAND_FSL_ELBC           1
 
-#define CONFIG_SYS_BR1_PRELIM          ( CONFIG_SYS_NAND_BASE \
+#define CONFIG_SYS_BR1_PRELIM  ( CONFIG_SYS_NAND_BASE \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8               /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V )                /* valid */
-#define CONFIG_SYS_OR1_PRELIM          ( 0xFFFF8000            /* length 32K */ \
+#define CONFIG_SYS_OR1_PRELIM  ( 0xFFFF8000            /* length 32K */ \
                                | OR_FCM_CSCT \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \