Merge branch '2019-11-20-env-migration'

[oweals/u-boot.git] / include / configs / MPC8313ERDB_NAND.h

diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index bbb9d4b936cb2d45e26f2835498f9a0da1f66227..4389d66dc0cbd7a222a49c8dd0ddb6510de1f366 100644 (file)
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -54,8 +54,6 @@
 #define CONFIG_VSC7385_ENET
 #define CONFIG_TSEC2
 
-#define CONFIG_SYS_IMMR                0xE0000000
-
 #if !defined(CONFIG_SPL_BUILD)
 #define CONFIG_DEFAULT_IMMR    CONFIG_SYS_IMMR
 #endif
@@ -69,9 +67,6 @@
  */
 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
 
-#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT          3       /* Arbiter repeat count (0-7) */
-
 /*
  * Device configurations
  */
@@ -91,9 +86,7 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
 
 /*
  * Manually set up DDR parameters, as this board does not
@@ -170,17 +163,6 @@
 #define CONFIG_SYS_FLASH_SIZE          8       /* flash size in MB */
 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* display empty sectors */
 
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                                       | BR_PS_16      /* 16 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_9 \
-                               | OR_GPCM_EHTR \
-                               | OR_GPCM_EAD)
-                               /* 0xFF006FF7   TODO SLOW 16 MB flash size */
-
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      135     /* sectors per device */
 
@@ -204,18 +186,6 @@
 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)    /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN  (512 * 1024)    /* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC   LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR    (0x00040000 /* TODO */ \
-                               | (0xFF << LBCR_BMT_SHIFT) \
-                               | 0xF)  /* 0x0004ff0f */
-
-                               /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR   0x20000000  /*TODO */
-
 /* drivers/mtd/nand/raw/nand.c */
 #if defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_NAND_BASE           0xFFF00000
@@ -230,21 +200,6 @@
 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR0_PRELIM  \
-                               (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
-                               | OR_FCM_CSCT \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
-                               /* 0xFFFF8396 */
-
 /* Still needed for spl_minimal.c */
 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
@@ -253,20 +208,7 @@
 #define CONFIG_SYS_BCSR_ADDR           0xFA000000
 #define CONFIG_SYS_BCSR_SIZE           (32 * 1024)     /* 0x00008000 */
                                        /* map at 0xFA000000 on LCS3 */
-#define CONFIG_SYS_BR3_PRELIM          (CONFIG_SYS_BCSR_ADDR \
-                                       | BR_PS_8       /* 8 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-                                       /* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV2 \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFF8FF7 */
+
 /* Vitesse 7385 */
 
 #ifdef CONFIG_VSC7385_ENET
@@ -275,19 +217,7 @@
 #define CONFIG_SYS_VSC7385_BASE                0xF0000000
 #define CONFIG_SYS_VSC7385_SIZE                (128 * 1024)    /* 0x00020000 */
 
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_VSC7385_BASE \
-                                       | BR_PS_8       /* 8 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_SETA \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFE09FF */
+
 #endif
 
 #define CONFIG_MPC83XX_GPIO 1
@@ -367,12 +297,7 @@
 /*
  * Environment
  */
-#define CONFIG_ENV_OFFSET              (512 * 1024)
-#define CONFIG_ENV_SECT_SIZE   CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-#define CONFIG_ENV_RANGE               (CONFIG_ENV_SECT_SIZE * 4)
-#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#define CONFIG_ENV_RANGE               (CONFIG_SYS_NAND_BLOCK_SIZE * 4)
 
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
@@ -413,13 +338,6 @@
                        /* Enable Internal USB Phy and GPIO on LCD Connector */
 #define CONFIG_SYS_SICRL       (SICRL_USBDR_10 | SICRL_LBC)
 
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
-                                HID0_ENABLE_INSTRUCTION_CACHE | \
-                                HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
 /*
  * Environment Configuration
  */