#define CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
-#define CONFIG_SYS_IMMR 0xE0000000
-
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
#endif
*/
#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
/*
* Device configurations
*/
/*
* DDR Setup
*/
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
/*
* Manually set up DDR parameters, as this board does not
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
- | (0xFF << LBCR_BMT_SHIFT) \
- | 0xF) /* 0x0004ff0f */
-
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
-
/* drivers/mtd/nand/raw/nand.c */
#if defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_NAND_BASE 0xFFF00000
/* Enable Internal USB Phy and GPIO on LCD Connector */
#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_INSTRUCTION_CACHE | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
/*
* Environment Configuration
*/