Support for redundant environment in NAND Flash.

[oweals/u-boot.git] / include / configs / MPC8260ADS.h

diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 61a1c271ab7ce367a1bb0b80689646ff4f091ebf..6195bca85ba92b517cc4de59d65e2a084753ee8d 100644 (file)
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -13,7 +13,7 @@
  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  * Ported to MPC8272ADS board.
  *
- * Copyright (c) 2005 MontaVista Software, Inc.   
+ * Copyright (c) 2005 MontaVista Software, Inc.
  * Vitaly Bordug <vbordug@ru.mvista.com>
  * Added support for PCI bridge on MPC8272ADS
  *
@@ -55,7 +55,6 @@
 #   define CFG_LOWBOOT         1
 #endif
 
-
 /* ADS flavours */
 #define CFG_8260ADS            1       /* MPC8260ADS */
 #define CFG_8266ADS            2       /* MPC8266ADS */
@@ -185,7 +184,6 @@
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 
-
 #ifndef CONFIG_SDRAM_PBI
 #define CONFIG_SDRAM_PBI       0 /* By default, use bank-based interleaving */
 #endif
@@ -334,7 +332,6 @@
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
 
-
 #ifdef CFG_LOWBOOT
 /* PQ2FADS flash HRCW = 0x0EB4B645 */
 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                      |\
@@ -386,13 +383,11 @@
 #  define CFG_ENV_SIZE         0x200
 #endif /* CFG_RAMBOOT */
 
-
 #define CFG_CACHELINE_SIZE     32      /* For MPC8260 CPU */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value */
 #endif
 
-
 #define CFG_HID0_INIT          0
 #define CFG_HID0_FINAL         (HID0_ICE | HID0_IFEM | HID0_ABE )
 
@@ -461,8 +456,6 @@
  * these windows.
  */
 
-
-
 /*
  * Master window that allows the CPU to access PCI Memory (prefetch).
  * This window will be setup with the second set of Outbound ATU registers
@@ -504,9 +497,13 @@
 #define CFG_PCI_MSTR0_LOCAL            CFG_PCI_MSTR_IO_LOCAL           /* Local base */
 #define CFG_PCIMSK0_MASK               ~(CFG_PCI_MSTR_IO_SIZE - 1U)    /* Size of window */
 /* PCIBR1 - prefetch and non-prefetch regions joined together */
-#define CFG_PCI_MSTR1_LOCAL            CFG_PCI_MSTR_MEM_LOCAL  
+#define CFG_PCI_MSTR1_LOCAL            CFG_PCI_MSTR_MEM_LOCAL
 #define CFG_PCIMSK1_MASK               ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
 
 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
 
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CONFIG_HAS_ETH1
+#endif
+
 #endif /* __CONFIG_H */