Switch from archive libraries to partial linking

[oweals/u-boot.git] / include / configs / M5235EVB.h

diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index e6c87efef0308968cb9db55d318d2ee49a3e0763..cd12d2b7a4f3c1755e5158b6a79dfd21ffd55e60 100644 (file)
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -167,10 +167,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
-#define CONFIG_SYS_INIT_RAM_END        0x10000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x10000 /* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL       0x21
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -197,6 +196,7 @@
  */
 /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTMAPSZ           (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN           (CONFIG_SYS_SDRAM_SIZE << 20)
 
 /*-----------------------------------------------------------------------
  * FLASH organization
@@ -215,13 +215,12 @@
 #      define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 #endif
 
-#define CONFIG_SYS_FLASH_BASE          (CONFIG_SYS_CS0_BASE << 16)
+#define CONFIG_SYS_FLASH_BASE          (CONFIG_SYS_CS0_BASE)
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
  */
 #define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_IS_EMBEDDED 1
 #ifdef NORFLASH_PS32BIT
 #      define CONFIG_ENV_OFFSET                (0x8000)
 #      define CONFIG_ENV_SIZE          0x4000
@@ -237,6 +236,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINV)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_CENB | CF_CACR_DISD | \
+                                        CF_CACR_CEIB | CF_CACR_DCM | \
+                                        CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
@@ -251,13 +262,13 @@
  * CS7 - Available
  */
 #ifdef NORFLASH_PS32BIT
-#      define CONFIG_SYS_CS0_BASE      0xFFC0
+#      define CONFIG_SYS_CS0_BASE      0xFFC00000
 #      define CONFIG_SYS_CS0_MASK      0x003f0001
-#      define CONFIG_SYS_CS0_CTRL      0x1D00
+#      define CONFIG_SYS_CS0_CTRL      0x00001D00
 #else
-#      define CONFIG_SYS_CS0_BASE      0xFFE0
+#      define CONFIG_SYS_CS0_BASE      0xFFE00000
 #      define CONFIG_SYS_CS0_MASK      0x001f0001
-#      define CONFIG_SYS_CS0_CTRL      0x1D80
+#      define CONFIG_SYS_CS0_CTRL      0x00001D80
 #endif
 
 #endif                         /* _M5329EVB_H */