NAND finally working. Two bugs fixed:

[oweals/u-boot.git] / include / configs / DU405.h

diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index 5a5415a13e9666e0d88b3b97c17713a3aac1089f..5489a539360c46e544f916734aa4ea484b34f920 100644 (file)
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -32,12 +32,14 @@
  * High Level Configuration Options
  * (easy to change)
  */
+#define CONFIG_IDENT_STRING     " $Name:  $"
 
 #define CONFIG_405GP           1       /* This is a PPC405 CPU         */
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
 #define CONFIG_DU405           1       /* ...on a DU405 board          */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* call board_early_init_f()    */
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
 
 #define CONFIG_SYS_CLK_FREQ    25000000 /* external frequency to pll   */
 
@@ -47,17 +49,21 @@
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND     "bootm fff00000"
 
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
 
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
                                CFG_CMD_PCI     | \
                                CFG_CMD_IRQ     | \
                                CFG_CMD_IDE     | \
                                CFG_CMD_ELF     | \
+                               CFG_CMD_MII     | \
                                CFG_CMD_DATE    | \
                                CFG_CMD_EEPROM  )
 
@@ -107,6 +113,8 @@
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
 
+#define CFG_RX_ETH_BUFFER      16      /* use 16 rx buffer on 405 emac */
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -215,7 +223,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                8192    /* For IBM 405 CPUs                     */
+#define CFG_DCACHE_SIZE                8192    /* For AMCC 405 CPUs                    */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */