Merge with /home/m8/git/u-boot

[oweals/u-boot.git] / include / configs / CATcenter.h

diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index 776fce5a9867957be993f6f784ef8c42162e42a6..7ec4599ebb5df33c8916ce3797ddb3c00f2d6b5e 100644 (file)
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -193,6 +193,8 @@
  */
 #define CFG_NAND0_BASE 0xFF400000
 #define CFG_NAND1_BASE 0xFF000000
+#define CFG_NAND_BASE_LIST     { CFG_NAND0_BASE }
+#define NAND_BIG_DELAY_US      25
 
 /* For CATcenter there is only NAND on the module */
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
@@ -218,9 +220,9 @@
 #define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 
 
-#define NAND_DISABLE_CE(nand) do \
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
 { \
-       switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+       switch((unsigned long)nandptr) \
        { \
            case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
@@ -231,9 +233,9 @@
        } \
 } while(0)
 
-#define NAND_ENABLE_CE(nand) do \
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
 { \
-       switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+       switch((unsigned long)nandptr) \
        { \
            case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
@@ -244,8 +246,7 @@
        } \
 } while(0)
 
-
-#define NAND_CTL_CLRALE(nandptr) do \
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -258,7 +259,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_SETALE(nandptr) do \
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -271,7 +272,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_CLRCLE(nandptr) do \
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -284,7 +285,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_SETCLE(nandptr) do { \
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
        switch((unsigned long)nandptr) { \
        case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
@@ -409,7 +410,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                16384   /* For IBM 405 CPUs, older 405 ppc's    */
+#define CFG_DCACHE_SIZE                16384   /* For AMCC 405 CPUs, older 405 ppc's   */
                                        /* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)