ARM: imx: ddr: Add missing PHY reset

[oweals/u-boot.git] / include / atmel_hlcdc.h

diff --git a/include/atmel_hlcdc.h b/include/atmel_hlcdc.h
index 945b30acb01b1969b56ddceba7d2c45394935da7..5e339f50f2665bd16ff0ea3a1579635969a96deb 100644 (file)
--- a/include/atmel_hlcdc.h
+++ b/include/atmel_hlcdc.h
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  *  Header file for AT91/AT32 MULTI LAYER LCD Controller
  *
  *  Data structure and register user interface
  *
  *  Copyright (C) 2012 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __ATMEL_HLCDC_H__
 #define __ATMEL_HLCDC_H__
@@ -217,6 +204,13 @@ struct atmel_hlcd_regs {
 #define LCDC_BASECFG3_RDEF(value) \
        ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
 
+#define LCDC_BASECLUT_BCLUT_Pos 0
+#define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos)
+#define LCDC_BASECLUT_GCLUT_Pos 8
+#define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos)
+#define LCDC_BASECLUT_RCLUT_Pos 16
+#define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos)
+
 #define LCDC_BASECFG4_DMA      (0x1 << 8)
 #define LCDC_BASECFG4_REP      (0x1 << 9)